Chapter 6 (Lect 3) Counters Continued. Unused States Ring counter. Implementing with Registers Implementing with Counter and Decoder

Transcription

1 Chapter 6 (Lect 3) Counters Continued Unused States Ring counter Implementing with Registers Implementing with Counter and Decoder

2 Sequential Logic and Unused States Not all states need to be used Can be used as don t care conditions Risk Entering unused state accidently Never returning to a valid state Solution Assign unused states Use unused states as don t cares--and test unused states of completed design--validate as self-correcting Self-correcting Name given to a sequential circuit that returns to a valid state after entering an unused state Note returning to a valid state may require more than one clock cycle

3 Unused States example: Want Current state A B C State Table Next state A B C J A K A J B K B J C K C X 0 X 1 X X 1 X X X X 1 0 X X 0 0 X 1 X X 0 1 X X X 1 X 1 0 X State Table and K-maps give J A = B K A = B J B = C K B = 1 J C = B K C = 1

4 Equations and Circuit J Clk K A 011 Check unused states J Clk K B 111 Q(t) Q(t+1) J K logic 1 J Clk K C X X 1 0 X X 0 clk

5 Ring Counters constructed from shift-registers or the combination of counters and decoders counters in general are frequently used to generate timing signals Examples Update--track-- update time in software 10 ms clock signal 4-bit counter (edge trigger) return to zero count = 160 ms elapsed Determining lapsed time of event Detecting input signal during which counter increments by 5 counts length signal detected = 50 ms Sequence events Read Value one Read Value two Add values one and two Write sum

6 CLK shift right Shift register ring counter: T 0 T 1 T 2 T 3 T 0 T 1 T 2 T 3 load 1 D Q D Q Q D Q D Clk Clk Clk Clk clock clock T 0 T 1 T 2 T 3

7 Counter and decoder configuration : enable 2-bit T 0 CLK counter s 1 2X4 T 1 decoder s 0 T 2 T 3 CLK cycle s 1 s 0 Decoder output T T T T 0

8 Given a 25 ms clock signal, is there a simple way to create a 100 ms clock signal from it?

9 Chapter 7 (Lect 2) Memory Random Access Memory (RAM) Read/Write operations Static and Dynamic Memory Decoding Coincident Decoding

10 Memory unit: is a collection of storage cells, and circuitry necessary for accessing, capable of storing a large quantity of binary information memory write Information written to -- for storage memory read Information read from -- for processing Random-access memory (RAM): can be used for both read and write operations Any arbitrary location in RAM requires the same time for a read or write operation

11 Memory units store binary information in groups of bits called words Memory words can represent any binary coded information 8-bits is called a byte Typically memory words are multiples of 8-bits 32-bit word contains 4-bytes Memory Capacity usually reported in total number of bytes it is capable of storing

12 Basic Memory unit n data input lines k address lines read 2 k n-bit words write n data output lines k-address lines: specify location where memory word will be written to or read from read: is a control input specifying information transferred from memory (nondestructive) write: is a control input specifying information transferred into memory

13 Each word is assigned a unique address in memory --From 0 to 2 k - 1, k = number of address lines --Each word is addressed by a k-bit number --Number of address bits needed 2 k m (here m = number of words) Examples: --capacity 1K 8 bit words (1K x 8) = 1K byte memory 2 k 1024, k = 10 --capacity 1 K 16 bit words (1K x 16) = 2K byte memory 2 k 1024, k = 10

14 Summary of Memory access: Write 1. Apply binary address at the address lines 2. Apply data at the data input lines 3. Enable the write control Read 1. Apply binary address at the address lines 2. Enable the read control It is important to note that a clock signal is not used for memory access, the CPU applies the address and control inputs. So the CPU must hold these signals, typically for multiple clock cycles, allowing the time needed to complete a read (access time) operation and a write (cycle time) operation. Most commercial memory implement a slightly different 2-line control Mem enable write/read action 0 X none 1 0 write 1 1 read

15 Static and Dynamic memory Static RAM (SRAM) Internal latches store the information, remains valid as long as power is applied Dynamic RAM (DRAM) Stores information in the form of electrical charges on capacitors, the charges must be periodically refreshed to remain valid DRAM -- offers lower power consumption and larger capacities SRAM -- simpler design and faster read/write access Other Topics: Flash memory and Solid State Hard drives

16 Memory Decoding: select input data input BC output word 0 read/write BC BC BC BC address lines word 1 2 x 4 decoder BC BC BC BC word 2 BC BC BC BC enable word 3 BC BC BC BC read/write output data

17 Coincident Decoding Recall a decoder with k inputs and 2 k outputs requires 2 k AND gates each having k inputs In memory decoding applications these numbers can get large quick The numbers can be reduced using two decoders in a two dimensional selection scheme Method: 1. Memory cells are arranged in a square array configuration 2. Two k/2 decoders are used: one selects row (half of the address), the other selects column (other half of address) Result for a 1K word memory 1-decoder 10 x 1024 = 1024 AND gates with 10 inputs each 2 -decoders 5 x 32 = 64 AND gates with 5 inputs each:

18 Coincident Decoding: x 32 decoder x 32 decoder address

19 What you should know 1. Be identify and check unused states 2. Know what a ring counter is and how it is useful 3. Understand how a counter and decoder is used to sequence events 4. Understand basic memory cell and how decoders are used to address