Memory Controller. Speaker: Tzu-Wei Tseng. Adopted from National Taiwan University SoC Design Laboratory. SOC Consortium Course Material

Transcription

1 Memory Controller Speaker: Tzu-Wei Tseng Adopted from National Taiwan University SoC Design Laboratory SOC Consortium Course Material

2 Goal of This Lab Familiarize with ARM memory interface Know ARM Integrator memory map well How to access memory

3 Outline The ARM Memory Interface [] ARM Integrator System Memory Map [2] [3] Lab Memory Control

4 Simple Memory Interface The simplest form of memory interface is suitable for operation with ROM and static RAM (SRAM). 8-bit memory types, so four parts of each type are required to form a 32-bit memory. Since the bottom two address lines, A[:], are used for byte selection, they are used by the control logic and not connected to the memory. Although the ARM performs reads of both bytes and words, the memory system can ignore the difference and always simply supply a word quantity.

5 Basic ARM Memory System ROMoe control RAMwe3 RAMwe2 RAMwe RAMwe various A[3:] RAMoe A[n+2:2] A[n+2:2] A[n+2:2] A[n+2:2] A[3:] ARM A[n:] oe we SRAM A[n:] oe we SRAM A[n:] oe we SRAM A[n:] oe we SRAM D[3:] D[7:] D[7:] D[7:] D[7:] D[3:] D[3:24] D[23:6] D[5:8] D[7:] D[7:] D[7:] D[7:] D[7:] ROM ROM ROM ROM oe A[n:] oe A[n:] oe A[n:] oe A[n:] A[m+2:2] A[m+2:2] A[m+2:2] A[m+2:2]

6 Control Logic It decides when to activate the ARM and when to activate the ROM A[3] = => access ROM A[3] = => access RAM It controls the byte write enables during a write operation Word write / half-word write / byte write It ensures that the data is ready before the processor continues The simplest solution is to run mclk slowly enough to ensure that all the memory devices can be accessed within a single clock cycle

7 Simple ARM Memory System Control Logic A[]A[] mas[] mas[] mclk RAMwe RAMwe RAMwe2 Write RAMwe3 r/w A[3] RAMoe ROMoe Read

8 Transfer Widths A[3] r/w mas[] mas[] A[] A[] Output signal ROMoe None Read RAMoe None Word (RAMwe, RAMwe, RAMwe2, RAMwe3) Half word (RAMwe, RAMwe) Write Half word (RAMwe2, RAMwe3) Byte (RAMwe) Byte (RAMwe) Byte (RAMwe2) Byte (RAMwe3)

9 DRAM memory organization ras latch decoder array of memory cells A[n:] latch mux cas data out ras: row address strobe cas: column address strobe

10 DRAM Timing Illustration mclk A[3:] A A+4 A+8 seq wait ras cas D[3:] N cycle S cycle S cycle

11 Outline The ARM Memory Interface [] ARM Integrator System Memory Map [2][3] Lab Memory Control

12 Core Module Memory Map The nmbdet signal is permanently grounded by the motherboard so that it is pulled LOW on the core module when it is fitted. The REMAP bit only has effect if the core module is attached to a motherboard (nmbdet = ).

13 Core Module Memory Map (cont.) 8MB 8MB 256MB 256KB

14 Core Module Alias Address

15 Memory Map for Core Module REMAP = : Default following reset. Accesses to addresses x to x3ffff S[] = ON: the access is to boot ROM S[] = OFF: the access is to flash REMAP = : Accesses to address x to x3ffff

16 Memory Map for Logic Modules S[] = ON: the EBI resources are mapped into the bottom 256MB of the system memory map. S[] = OFF: the flash is mapped repeatedly into bottom 256MB of the system memory map.

17 System Memory Map (/3)

18 System Memory Map (2/3)

19 System Memory Map (3/3)

20 Outline The ARM Memory Interface ARM Integrator System Memory Map Lab Memory Control

21 Lab 7: Memory Controller Goal Realize the principle of memory map and internal and external memory Principles System memory map Core Module Control Register Core Module Memory Map Guidance We use a simple program to lead student understanding the memory. Requirements and Exercises Compare the performance between using SSRAM and SDRAM Discussion Discuss the following items about Flash, RAM, and ROM. Speed Capacity Internal /External

22 References [] [] ARM System-on-Chip Architecture by S.Furber, Addison Wesley Longman: ISBN [2] DUI98B_AP_UG.pdf. [3] DUI26B_CM7TDMI_UG.pdf