EECS 366: Computer Architecure. Memory Technology. Lecture Notes # 15. University of Illinois at Chicago. Instructor: Shantanu Dutt Department of EECS

Transcription

1 EECS 366: Computer Architecure Instructor: Shantanu Dutt Department of EECS University of Illinois at Chicago Lecture Notes # 15 Memory Technology c Shantanu Dutt

2 MEMORY ORGANIZATION Physical Characteristics of Memory Basically, all semiconductor storage devices are either static or dynamic In a dynamic device the storage is in terms of the presence or absence of a charge on a small capacitance In a static device (ex., a flip flop), stored information is due to the state of conduction or no conduction of a transistor Static devices need more power (for having a transistor continuously on), but can hold information indefinitely. Static devices also take up more space. They are, however, faster to read and write to Dynamic devices use low power and are smaller, but need periodic refreshment of the stored charge, which may be lost due to leakage. Also, reads are destructive.

3 (a) DRAM cell & read/write control of row i 1-bit of row register (b) 2-D organization of a 2^(m+n)-bit memory chip with 1-bit word dwrite dread & phi_1 & phi_2 NOTE: dread and dwrite are signals generated internally by the memory chip in response to external read/write or for refresh n-bit col. addr. Column Decoder read OR write 1 bit of addressed word Row Register GND data C 2^n rows m-bit row addr. Row Decoder i th output of row decoder control 2^m cols (bits) read OR write DRAM cell and Organization of 1-bit word memory chips

4 Organization of Memory System For a 32-bit word memory, for example, 32 of the 1-bit word memory chips chips are used, all fed by the same address lines. CPU-Memory Address Bus bit CPU-Memory Data Bus bit 2 1 Mbit chips bit 1 bit 0 1M Word (4M Byte) Memory Based on 1M-bit Chips and 32-bit Word Size

5 Read Control in a DRAM chip Read is destructive Need to write back data read to entire row of words (of 1 bit each) Timing diagram: i th output of row decoder control phi_1 data C phi_2 Read Row i GND dread Address Address valid (row i, col j) WB Row i rewrite Data Data Valid dwrite dread & phi_1 & phi_2 1-bit of row register (a) DRAM cell & read/write control of row i NOTE: dread and dwrite are signals generated internally by the memory chip in response to external read/write or for refresh (b) Read and Write Back Timing

6 (1) Block Refresh: Do a block refresh every until a critical time is reached when all refreshes have to be completed before any more r/w requests can be serviced. This reduces the average (2) Relaxed Refresh: Start refreshing at a time interval secs after the previous refresh started. Allow r/w access in the refresh period, requests in a refresh period are serviced only after refreshing is complete. Max. latency is, where is the time to read a single word, and is the propagation delay on the memory bus. The average latency or access time microseconds. Any r/w To refresh, either: Let of a memory element, and let all rows. Obviously, the organization should be such that otherwise memory access latency will be very high., be the max. time interval be the allowable time taken between to finish consecutive refreshing refreshes Every few milliseconds, the DRAM controller has to start refreshing all the rows before the data irreversibly leaks out. Two main refresh strategies can be used for this purpose. Refresh Control in a DRAM Chip

7 ! after a read 3. because the time required to restore or write back a row " 1. Access time: Time to get a read data back from memory 2. Cycle time: The min. time between 2 successive memory accesses Difference between access time and cycle time : max. latency for r/w access.

8 Refresh Control in a DRAM Chip (contd.) Timing Diagram: i th output of row decoder control phi_1 data C phi_2 Read Row i Read Row i+1 Read Row i+2 GND dread Address Row Address i Row Address i+1 Row Address i+2 WB Row i-1 WB Row i WB Row i+1 WB Row i+2 rewrite dwrite dread & phi_1 & phi_2 1-bit of row register NOTE: dread and dwrite are signals generated internally by the memory chip in response to external read/write or for refresh (b) Refresh Timing (a) DRAM cell & read/write control of row i

9 Physical Characteristics of RAMs The DRAM is an asynchronous unit, since it cannot be deterministically determined the r/w will take exactly so much time to complete (since, the DRAM could be refreshing at any time). Thus an acknowledge or ack signal (wait signal in the myth8 is required from the DRAM unit to the processor on completion of r/w operations Access becomes slower as size (in number of words) increases, because: (1) Bit lines become longer thus requiring more time for read or write data to settle (2) Address lines (row select and column select) become longer, again requiring more time for the select signal to settle

10 $ # Disadvantage: More hardware required in terms of bit lines, pass transistors, sense amplifiers, etc. ( vs. 1) ) ) # ) Main advantage: Refreshing is faster a row of words rather than single words are refreshed at a time. Refresh time complexity is for a organization vs. for 1-dim. ( *) org. $ ( Similarly, bit/data lines are shorter, and hence faster Row/Column decoders are faster Smaller decoder complexity: For row-col. organization, decoder complexity is for 1-dim. decoding. For ', the complexity of 2-dim. decoding is almost a square-root of the complexity of 1-dim. decoding! $ vs. $ % & # Why two-dimensional (row and column) decoding? Physical Organization of RAMs