Polusabirač. design.vhd. testbench.vhd. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
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1 Polusabirač design.vhd use ieee.numeric_std.all; entity half_adder is i_bit1 : in std_logic; i_bit2 : in std_logic; o_sum : out std_logic; o_carry : out std_logic end half_adder; architecture rtl of half_adder is o_sum <= i_bit1 xor i_bit2; o_carry <= i_bit1 and i_bit2; testbench.vhd use ieee.numeric_std.all; entity half_adder_tb is end half_adder_tb; architecture behave of half_adder_tb is signal r_bit1 : std_logic := '0'; signal r_bit2 : std_logic := '0'; signal w_sum : std_logic; signal w_carry : std_logic; UUT : entity work.half_adder uses default binding i_bit1 => r_bit1, i_bit2 => r_bit2, o_sum => w_sum,
2 o_carry => w_carry process is r_bit1 <= '0'; r_bit2 <= '0'; r_bit1 <= '0'; r_bit2 <= '1'; r_bit1 <= '1'; r_bit2 <= '0'; r_bit1 <= '1'; r_bit2 <= '1'; end process; end behave; Simulacija Pun sabirač
3 Design.vhd use ieee.numeric_std.all; entity full_adder is i_bit1 : in std_logic; i_bit2 : in std_logic; i_carry : in std_logic; o_sum : out std_logic; o_carry : out std_logic end full_adder; architecture rtl of full_adder is signal w_wire_1 : std_logic; signal w_wire_2 : std_logic; signal w_wire_3 : std_logic; w_wire_1 <= i_bit1 xor i_bit2; w_wire_2 <= w_wire_1 and i_carry; w_wire_3 <= i_bit1 and i_bit2; o_sum <= w_wire_1 xor i_carry; o_carry <= w_wire_2 or w_wire_3; FYI: Code above using wires will produce the same results as: o_sum <= i_bit1 xor i_bit2 xor i_carry; o_carry <= (i_bit1 xor i_bit2) and i_carry) or (i_bit1 and i_bit2 Wires are just used to be explicit. testbench.vhd SAMOSTALAN RAD
4 Ripple Carry Adder Design.vhd entity ripple_carry_adder_2_fa is i_add_term1 : in std_logic_vector(1 downto 0 i_add_term2 : in std_logic_vector(1 downto 0 o_result : out std_logic_vector(2 downto 0) end ripple_carry_adder_2_fa; architecture rtl of ripple_carry_adder_2_fa is component full_adder is i_bit1 : in std_logic; i_bit2 : in std_logic; i_carry : in std_logic; o_sum : out std_logic; o_carry : out std_logic end component full_adder; signal w_carry : std_logic_vector(2 downto 0 signal w_sum : std_logic_vector(1 downto 0 w_carry(0) <= '0'; adder no carry input on first full FULL_ADDER_1_INST : full_adder i_bit1 => i_add_term1(0), i_bit2 => i_add_term2(0), i_carry => w_carry(0), o_sum => w_sum(0), o_carry => w_carry(1)
5 FULL_ADDER_2_INST : full_adder i_bit1 => i_add_term1(1), i_bit2 => i_add_term2(1), i_carry => w_carry(1), o_sum => w_sum(1), o_carry => w_carry(2) o_result <= w_carry(2) & w_sum; VHDL Concatenation testbench.vhd entity ripple_carry_adder_tb is end ripple_carry_adder_tb; architecture rtl of ripple_carry_adder_tb is constant c_width : integer := 2; signal r_add_1 : std_logic_vector(c_width-1 downto 0) := (others => '0' signal r_add_2 : std_logic_vector(c_width-1 downto 0) := (others => '0' signal w_result : std_logic_vector(c_width downto 0 component ripple_carry_adder is generic ( g_width : natural i_add_term1 : in std_logic_vector(g_width-1 downto 0 i_add_term2 : in std_logic_vector(g_width-1 downto 0 o_result : out std_logic_vector(g_width downto 0) end component ripple_carry_adder; Instantiate the Unit Under Test (UUT) UUT : ripple_carry_adder generic map ( g_width => c_width ) i_add_term1 => r_add_1, i_add_term2 => r_add_2, o_result => w_result Test bench is non-synthesizable
6 process is r_add_1 <= "00"; r_add_2 <= "01"; r_add_1 <= "10"; r_add_2 <= "01"; r_add_1 <= "01"; r_add_2 <= "11"; r_add_1 <= "11"; r_add_2 <= "11"; end process;
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