Design Examples. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning
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1 Design Examples ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Cengage Learning
2 BCD to 7-Segment Display 418_04 2
3 BCD to 7-Segment Display entity BCD_Seven is port(bcd: in std_logic_vector(3 downto 0); Seven: out std_logic_vector(7 downto 1)); end BCD_Seven; architecture Behave of BCD_Seven is begin process(bcd) begin 418_04 3
4 BCD to 7-Segment Display case BCD is when "0000" => Seven <= " "; when "0001" => Seven <= " "; when "0010" => Seven <= " "; when "0011" => Seven <= " "; when "0100" => Seven <= " "; when "0101" => Seven <= " "; when "0110" => Seven <= " "; when "0111" => Seven <= " "; when "1000" => Seven <= " "; when "1001" => Seven <= " "; when others => null; end case; end process; end Behave; 418_04 4
5 Synchronization & Debouncing 418_04 5
6 Single Pulser 418_04 6
7 Behavioral Model entity PULSE is port(sw, CLK: in std_logic; SP: out std_logic); end PULSE; architecture Behave of PULSE is signal Sync: std_logic_vector(2 downto 0) := "000"; begin process(clk) begin if rising_edge(clk) then Sync <= SW & Sync(2) & Sync(1); end if; end process; SP <= Sync(1) and not Sync(0); end Behave; 418_04 7
8 VHDL Test Bench entity Pulse_Test is end Pulse_Test; architecture Behave of Pulse_Test is component PULSE port(sw, CLK: in std_logic; SP: out std_logic); end component; signal SW, CLK: std_logic := '0'; signal SP: std_logic; constant CLK_period: time := 100 ns; begin uut: PULSE port map(sw, CLK, SP); 418_04 8
9 VHDL Test Bench -- Stimulus process stim_proc: process begin wait for 48.5 ns; for I in 1 to 12 loop SW <= not SW; wait for 1 ns; end loop; SW <= '1'; wait for 485 ns; for I in 1 to 10 loop SW <= not SW; wait for 1 ns; end loop; SW <= '0'; wait; end process; 418_04 9
10 VHDL Simulation 418_04 10
11 VHDL Simulation 418_04 11
12 Adders Ripple-Carry Adder Concatenation of Full Adders Carry Look-Ahead Adder Fast Adder Carry signals calculated in advance Serial Adder Single Full Adder Shift and add one bit at a time 418_04 12
13 Ripple-Carry Adder 418_04 13
14 Carry Look-Ahead Adder 418_04 14
15 418_04 15 Carry Look-Ahead (CLA) i i i i i i i i i i C B A A B C C B A S ) ( 1 i i i i i i B A P A B G Generate (both 1) Propagate (either 1) i i i i i i i PC G C C P S 1
16 4-bit CLA Adder C C C C 1 G0 P0 C0 2 G1 PC 1 1 G1 PG 1 0 PP 1 0C0 3 G2 P2 C2 G2 P2 G1 P2 PG 1 0 P2 PP 1 0C0 4 G3 PC 3 3 G3 PG 3 2 P3 P2 G1 P3 P2 PG 1 0 P3 P2 PP 1 0C0 Limited by fan-in 418_04 16
17 16-bit CLA Adder 418_04 17
18 16-bit CLA Adder entity CLA16 is port(a, B: in std_logic_vector(15 downto 0); Ci: in std_logic; S: out std_logic_vector(15 downto 0); Co, PG, GG: out std_logic); end CLA16; 418_04 18
19 16-bit CLA Adder architecture Structure of CLA16 is component CLA4 port(a, B: in std_logic_vector(3 downto 0); Ci: in std_logic; S: out std_logic_vector(3 downto 0); Co, PG, GG: out std_logic); end component; component CLALogic is port(g, P: in std_logic_vector(3 downto 0); Ci: in std_logic; C: out std_logic_vector(3 downto 1); Co, PG, GG: out std_logic); end component; 418_04 19
20 16-bit CLA Adder signal G, P: std_logic_vector(3 downto 0); signal C: std_logic_vector(3 downto 1); begin CarryLogic: CLALogic port map(g, P, Ci, C, Co, PG, GG); ADD0: CLA4 port map(a(3 downto 0), B(3 downto 0), Ci, S(3 downto 0), open, P(0), G(0)); ADD1: CLA4 port map(a(7 downto 4), B(7 downto 4), C(1), S(7 downto 4), open, P(1), G(1)); ADD2: CLA4 port map(a(11 downto 8), B(11 downto 8), C(2), S(11 downto 8), open, P(2), G(2)); ADD3: CLA4 port map(a(15 downto 12), B(15 downto 12), C(3), S(15 downto 12), open, P(3), G(3)); end Structure; 418_04 20
21 Behavioral Model library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Adder_Behave16 is Port ( A : in std_logic_vector (15 downto 0); B : in std_logic_vector (15 downto 0); Ci : in std_logic; S : out std_logic_vector (15 downto 0); Co : out std_logic); end Adder_Behave16; 418_04 21
22 Behavioral Model architecture Behave of Adder_Behave16 is signal sum17: std_logic_vector(16 downto 0); begin sum17 <= ('0' & A) + ( 0 & B) + (X 0000 & Ci); S <= sum17(15 downto 0); Co <= sum17(16); end Behave; 418_04 22
23 FPGA Synthesis Results Adder Type Ripple-Carry CLA Behavioral Number of LUTs Combinational Path Delay (ns) Levels of Logic _04 23
24 Serial Adder 418_04 24
25 Adder Comparison 418_04 25
26 Data Path and Controller 418_04 26
27 Add-and-Shift Multiplier 4-bit Multiplicand 4-bit Multiplier 8-bit Product 4-bit Adder Controller 418_04 27
28 Add-and-Shift Multiplier 418_04 28
29 Multiplier Control 418_04 29
30 Behavioral Model library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Mult4X4 is port(clk, St: in std_logic; Mplier, Mcand: in std_logic_vector(3 downto 0); Product: out std_logic_vector(7 downto 0); Done: out std_logic); end Mult4X4; 418_04 30
31 Behavioral Model architecture Behave3 of Mult4X4 is signal State, NextState: integer range 0 to 9; signal Load, Sh, Ad: std_logic; signal ACC: std_logic_vector(8 downto 0); alias M: std_logic is ACC(0); begin control_logic: process(state, St, M) begin Load <= '0'; Sh <= '0'; Ad <= '0'; Done <= '0'; 418_04 31
32 Behavioral Model case State is when 0 => if St = '1' then Load <= '1'; NextState <= 1; else NextState <= 0; end if; when => if M = '1' then Ad <= '1'; NextState <= State + 1; else Sh <= '1'; NextState <= State + 2; end if; 418_04 32
33 Behavioral Model when => Sh <= '1'; NextState <= State + 1; when 9 => Done <= '1'; NextState <= 0; end case; end process; control_regs: process(clk) begin if rising_edge(clk) then State <= NextState; end if; end process; 418_04 33
34 Behavioral Model datapath: process(clk) begin if rising_edge(clk) then if Load = '1' then ACC(8 downto 4) <= "00000"; ACC(3 downto 0) <= Mplier; end if; if Ad = '1' then ACC(8 downto 4) <= ACC(8 downto 4) + Mcand; end if; 418_04 34
35 Behavioral Model if Sh = '1' then ACC <= '0' & ACC(8 downto 1); end if; end if; end process; Product <= ACC(7 downto 0); end Behave3; 418_04 35
36 VHDL Simulation 418_04 36
37 FPGA Implementation Xilinx Spartan3e 100K System Gates 50 MHz Clock ChipScope Pro Virtual Input/Output Core (VIO) Integrated Logic Analyzer (ILA) Real-Time Verification Captures On-chip Signals Off-chip Analysis via JTAG Programming Cable 418_04 37
38 VHDL Test Bench entity testmult4x4 is port(clk: in std_logic); end testmult4x4; architecture test1 of testmult4x4 is component mult4x4 port(clk, St: in std_logic; Mplier, Mcand: in std_logic_vector(3 downto 0); Product: out std_logic_vector(7 downto 0); Done: out std_logic); end component; 418_04 38
39 VHDL Test Bench component ila port(control: in std_logic_vector(35 downto 0); clk: in std_logic; trig0: in std_logic_vector(17 downto 0)); end component; component vio port(control: in std_logic_vector(35 downto 0); clk: in std_logic; sync_in: in std_logic_vector(8 downto 0); sync_out: out std_logic_vector(8 downto 0)); end component; 418_04 39
40 VHDL Test Bench signal... signal... begin mult1: mult4x4 port map(clk, St, Mplier, Mcand, Product, Done); i_ila: ila port map(control0, clk, trig0); i_vio: vio port map(control1, clk, sync_in, sync_out); 418_04 40
41 VHDL Test Bench trig0(17) <= st; trig0(16 downto 13) <= Mplier; trig0(12 downto 9) <= Mcand; trig0(8 downto 1) <= Product; trig0(0) <= Done; sync_in(8 downto 1) <= Product; sync_in(0) <= Done; St <= sync_out(8); Mplier <= sync_out(7 downto 4); Mcand <= sync_out(3 downto 0); end test1; 418_04 41
42 ChipScope Pro Analyzer 418_04 42
43 Array Multiplier 418_04 43
44 Array Multiplier 418_04 44
45 VHDL Simulation 418_04 45
46 Hardware Requirements n-bit Multiplication (2n-bit Product) n 2 And Gates (n-1) x n-bit Adders 16-bit Multiplication 256 And Gates 15 x 16-bit Adders 32-bit Multiplication 1024 And Gates 31 x 32-bit Adders 418_04 46
47 Signed Multiplication Signed Binary Fractions 2's Complement S.XXX ±. 1 / 2 1 / 4 1 / 8 Four Cases _04 47
48 2's Complement Multiplier 418_04 48
49 Multiplier Control 418_04 49
50 Faster Multiplier 418_04 50
51 Multiplier Control 418_04 51
52 Behavioral Model library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Mult2C is port(clk, St: in std_logic; Mplier, Mcand: in std_logic_vector(3 downto 0); Product: out std_logic_vector (6 downto 0); Done: out std_logic); end Mult2C; 418_04 52
53 Behavioral Model architecture Behave3 of Mult2C is signal State, Nextstate: integer range 0 to 5; signal A, B, compout, addout: std_logic_vector(3 downto 0); signal AdSh, Sh, Load, Cm: std_logic; alias M: std_logic is B(0); begin control_logic: process(state, St, M) begin Load <= '0'; AdSh <= '0'; Sh <= '0'; Cm <= '0'; Done <= '0'; 418_04 53
54 Behavioral Model case State is when 0 => if St = '1' then Load <= '1'; Nextstate <= 1; else Nextstate <= 0; end if; when => -- "add/shift" State if M = '1' then AdSh <= '1'; else Sh <= '1'; end if; Nextstate <= State + 1; 54
55 Behavioral Model when 4 => if M = '1' then Cm <= '1'; AdSh <= '1'; else Sh <= '1'; end if; Nextstate <= 5; when 5 => Done <= '1'; Nextstate <= 0; end case; end process; -- add complement if sign 418_04 55
56 Behavioral Model control_regs: process(clk) begin if rising_edge(clk) then State <= Nextstate; end if; end process; -- datapath compout <= not Mcand when Cm = '1' else Mcand; addout <= A + compout + Cm; 418_04 56
57 Behavioral Model datapath: process(clk) begin if rising_edge(clk) then if Load = '1' then A <= "0000"; B <= Mplier; end if; if AdSh = '1' then A <= compout(3) & addout(3 downto 1); B <= addout(0) & B(3 downto 1); end if; 418_04 57
58 Behavioral Model if Sh = '1' then A <= A(3) & A(3 downto 1); B <= A(0) & B(3 downto 1); end if; end if; end process; Product <= A(2 downto 0) & B; end Behave3; 418_04 58
59 Test Bench constant Mcandarr: arr := ( "0100", "1100", "1100", "0010", "0010"); constant Mplierarr: arr := ( "0110", "0110", "1010", "0101", "1011"); constant Productarr: arr2 := (" ", "," "," "," "); 418_04 59
60 Test Bench stim_proc: process begin for i in 1 to N loop Mcand <= Mcandarr(i); Mplier <= Mplierarr(i); St <= '1'; wait until rising_edge(clk); St <= '0'; wait until falling_edge(done); assert Product = Productarr(i) report "Incorrect Product" severity error; end loop; report "TEST COMPLETED"; end process; 418_04 60
61 VHDL Simulation 418_04 61
62 Summary Design Examples BCD to 7-Segment Display Adders Multipliers VHDL Models VHDL Test Benches FPGA Implementations ChipScope Pro 418_04 62
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