Cyclone II. Part 2 PLLs, Multipliers, and IOs
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1 Cyclone II Part 2 PLLs, Multipliers, and IOs
2 Phase Locked Loop Designed to match an output signal to the frequency and phase of an input signal Signals must be periodic (clocks) By using input and feedback dividers the PLL can create an output that is a fractional frequency of the input F out = F in m n 2 tj
3 Phase Locked Loop Simplified block diagram error detector Fref 1/N + - e(s) LPF VCO F out θ out 1/M Out of Lock Frequency Locked Phase out of Lock Frequency and Phase Locked + input - input up down I out LPF Output 3 tj
4 Phase Locked Loop Cyclone II EP2C20 4 PLLs Src: Cyclone II Device Handbook 4 tj
5 Phase Locked Loop Features M/N divider M: 1-32, N: 1-4 Post-scale counter (c) 1 to 32 Single or differential input 3 internal logic outputs/pll 1 external (pin) output/pll Lock signal Extensive multiplexing Phase shift capability Programmable output duty cycle 5 tj
6 Phase Locked Loop Cyclone II EP2C20 F out = F in m n 1 c Src: Cyclone II Device Handbook 6 tj
7 Phase Locked Loop Signals Clock Input(s) Clock Outputs Lock Output pllena PLL enable areset PLL reset Clears counters pfdena Turns off the charge pumps VCO continues to operate but no longer updates clkswitch Allows manual clock switchover Src: Cyclone II Device Handbook 7 tj
8 Phase Locked Loop Normal Mode Operation Clock signal at register inputs is phase locked External clock signal may lead or lag the internal signals Src: Cyclone II Device Handbook 8 tj
9 Phase Locked Loop Zero Delay Buffer Mode Operation Clock signal at output pin is phase locked Internal clock signal at the register inputs may lead or lag the input signal Src: Cyclone II Device Handbook 9 tj
10 Phase Locked Loop No Compensation Mode Operation PLL is locked but no compensation made for clock loads/paths Lowest jitter configuration Src: Cyclone II Device Handbook 10 tj
11 Phase Locked Loop Source Synchronous Mode Operation Data/Clk phase relationship maintained Input/Output phase relationship is lost Src: Cyclone II Device Handbook 11 tj
12 Phase Locked Loop Programmable Duty Cycle Output duty cycle can be programmed Granularity = 50% / Count Count is a setting on the post scale counter High, low count value Programmable Phase Shift Coarse and Fine shifting 12 tj
13 Phase Locked Loop Multiplexing Src: Cyclone II Device Handbook 13 tj
14 Phase Locked Loop Multiplexing Src: Cyclone II Device Handbook 14 tj
15 MegaFunction AltPll 15 tj
16 MegaFunction AltPll 16 tj
17 MegaFunction AltPll 17 tj
18 MegaFunction AltPll 18 tj
19 MegaFunction AltPll 19 tj
20 MegaFunction AltPll 20 tj
21 LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY plla IS END plla; ARCHITECTURE SYN OF plla IS BEGIN PORT ( ); SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT altpll GENERIC ( ); PORT ( ); END COMPONENT; sub_wire5_bv(0 DOWNTO 0) <= "0"; sub_wire5 <= To_stdlogicvector(sub_wire5_bv); locked <= sub_wire0; sub_wire2 <= sub_wire1(0); c0 <= sub_wire2; sub_wire3 <= inclk0; sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; altpll_component : altpll GENERIC MAP ( ) PORT MAP ( ); areset : IN STD_LOGIC := '0'; inclk0 : IN STD_LOGIC := '0'; pllena : IN STD_LOGIC := '1'; c0 : OUT STD_LOGIC ; locked : OUT STD_LOGIC clk0_divide_by clk0_duty_cycle clk0_multiply_by clk0_phase_shift compensate_clock gate_lock_signal inclk0_input_frequency intended_device_family invalid_lock_multiplier lpm_hint lpm_type operation_mode port_activeclock port_areset port_clkbad0 port_clkbad1 port_clkloss port_clkswitch port_configupdate port_fbin port_inclk0 port_inclk1 port_locked port_pfdena port_phasecounterselect port_phasedone port_phasestep port_phaseupdown port_pllena port_scanaclr port_scanclk port_scanclkena port_scandata port_scandataout port_scandone port_scanread port_scanwrite port_clk0 port_clk1 port_clk2 port_clk3 port_clk4 port_clk5 port_clkena0 port_clkena1 port_clkena2 port_clkena3 port_clkena4 port_clkena5 port_extclk0 port_extclk1 port_extclk2 port_extclk3 valid_lock_multiplier clk0_divide_by => 1, clk0_duty_cycle => 35, clk0_multiply_by => 1, clk0_phase_shift => "0", compensate_clock => "CLK0", gate_lock_signal => "NO", inclk0_input_frequency => 10000, intended_device_family => "Cyclone II", invalid_lock_multiplier => 5, lpm_hint => "CBX_MODULE_PREFIX=plla", lpm_type => "altpll", operation_mode => "NORMAL", port_activeclock => "PORT_UNUSED", port_areset => "PORT_USED", port_clkbad0 => "PORT_UNUSED", port_clkbad1 => "PORT_UNUSED", port_clkloss => "PORT_UNUSED", port_clkswitch => "PORT_UNUSED", port_configupdate => "PORT_UNUSED", port_fbin => "PORT_UNUSED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_UNUSED", port_locked => "PORT_USED", port_pfdena => "PORT_UNUSED", port_phasecounterselect => "PORT_UNUSED", port_phasedone => "PORT_UNUSED", port_phasestep => "PORT_UNUSED", port_phaseupdown => "PORT_UNUSED", port_pllena => "PORT_USED", port_scanaclr => "PORT_UNUSED", port_scanclk => "PORT_UNUSED", port_scanclkena => "PORT_UNUSED", port_scandata => "PORT_UNUSED", port_scandataout => "PORT_UNUSED", port_scandone => "PORT_UNUSED", port_scanread => "PORT_UNUSED", port_scanwrite => "PORT_UNUSED", port_clk0 => "PORT_USED", port_clk1 => "PORT_UNUSED", port_clk2 => "PORT_UNUSED", port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", port_clkena1 => "PORT_UNUSED", port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED", port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED", port_extclk0 => "PORT_UNUSED", port_extclk1 => "PORT_UNUSED", port_extclk2 => "PORT_UNUSED", port_extclk3 => "PORT_UNUSED", valid_lock_multiplier => 1 areset => areset, pllena => pllena, inclk => sub_wire4, locked => sub_wire0, clk => sub_wire1 : NATURAL; : NATURAL; : NATURAL; : NATURAL; : NATURAL; : NATURAL areset : IN STD_LOGIC ; clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); locked : OUT STD_LOGIC ; pllena : IN STD_LOGIC ; inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) PLLs MegaFunction AltPll 21 tj
22 Multipliers Multipliers Embedded Blocks within the chip dedicated to multiplication 1-18b x 18b or 2 9b x 9b multipliers per block EP2C20 has 26 multiplier blocks Src: Cyclone II Device Handbook 22 tj
23 Multipliers Multipliers Embedded Signals signa sign of A signb sign of B aclr clear registers clock ena - enable Src: Cyclone II Device Handbook 23 tj
24 Multipliers Multipliers Embedded 18 x 18 mode Src: Cyclone II Device Handbook 24 tj
25 Multipliers Multipliers Embedded 9 x 9 mode Common signa signb aclr clock ena 25 Src: Cyclone II Device Handbook tj
26 Multipliers Multipliers Embedded MegaWizard lpm_mult standard multiplier altmult_add uses LEs to implement the adders in multiply/add function altmult_accum uses LEs to implement the accumulator in a multiply/accumulate function 26 tj
27 Multipliers Multipliers Lpm_mult 27 tj
28 Multipliers Multipliers Lpm_mult 28 tj
29 Multipliers Multipliers Lpm_mult 29 tj
30 Multipliers Multipliers Lpm_mult 30 tj
31 Multipliers Multipliers Lpm_mult 31 tj
32 Multipliers Multipliers Lpm_mult 32 tj
33 Multipliers Multipliers Soft Multipliers RAM based Look Up Table All possible solutions stored Used for constant coefficient multiplication Logic based 33 tj
34 I/O Input/Outputs EP2C20 8 I/O banks Src: Cyclone II Device Handbook 34 tj
35 I/O Input/Outputs Multiple Configurations Src: Cyclone II Device Handbook 35 tj
36 I/O Input/Outputs Multiple Configurations Programmable Current Strength Programmable Slew Rate Control Programmable Open Drain Output Programmable Bus Hold Programmable Pull Up Resistor PCI Clamp Diode On Chip Termination Programmable Delay 36 tj
37 I/O Input/Outputs Support a wide range of standards Src: Cyclone II Device Handbook 37 tj
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