SDRAM Interface Clocking for the NB3000
|
|
|
- Georgina Dean
- 5 years ago
- Views:
Transcription
1 SDRAM Interface Clocking for the NB3000 Frozen Content Modified by on 6-Nov-2013 NB3000XN 1. Schematic wiring for Xilinx DCM clocks. 2. Shared Memory Port PlugIn wiring. NB3000AL 1. Altera PLL wiring.
2 2. Shared Memory Port PlugIn wiring Step by step Clock manager generation: NanoBoard 3000 Xilinx version Wishbone Clock and Sdram Memory controller clock generation 1. Start CoreGenerator from ISE Accessories menu. 2. Go to FILE->NEW PROJECT and browse to your project location. Type in project name "MainClock" and save your project. 3. In the project options dialog select family, device, package and speed grade.
3 Figure 1. Launching the Xilinx Core Generator to generate the SDRAM Clock Manager. Click OK button. 4. Browse to "FPGA Features and Design/Clocking/Spartan-3E, Spartan-3A/Single DCM_SP" component and double click it.
4 Figure 2. Select the DCM (Digital Clock Manager) option. 5. Provide Component name: MainClock and hit OK button. Figure 3. Specify the name for the new DCM. 6. Select Output file type and XST as Synthesis Tool.
5 Figure 4. Select the output file type and synthesis tool. 7. General Setup page. Provide input clock frequency and enable CLK2X output port. CLK0 output becomes our Wishbone Clock and CLK2X is a copy of it with frequency multiplied by 2. This is our Memory Controller clock that we use internally in FPGA. LOCKED output will give us indication when the DCM is 'locked' to input clock indicating that all outputs are stable. "CLKIN Source" and "Feedback Source" group boxes allow us to enable IOB buffer insertion as well as internal feedback clock buffering via BUFG. This is Xilinx specific and is automatically done by Altium Designer when you build your design. We can set both to 'internal'.
6 Figure 5. Configure Digital Clock Manager. Click Next. 8. Select Use Global Buffers for all selected clock outputs option. This will insert Xilinx clock buffers in the output forcing place and route tool to place our clocks on dedicated global clock lines.
7 Figure 6. Enable Global Buffers for all output clocks. Click Next. 9. Review all options and click on Finish button. This will produce our MainClock.vhd file which we can add to our design.
8 Figure 7. Review configuration and generate output files. Sdram Clock Board Deskew DCM 1. Go FILE->NEW PROJECT and browse to your project location. Type in project name "SdramBoardDeskew" and save your project. 2. in the project options dialog select family, device, package and speed grade.
9 Figure 8. Configure the Core Generator for Spartan 3AN target. 4. Browse to "FPGA Features and Design/Clocking/Spartan-3E, Spartan-3A/Single DCM_SP" component and double click it.
10 Figure 9.Select the DCM (Digital Clock Manager) option. 5. Provide Component name: SdramBoardDeskew and hit OK button. Figure 10. Specify the name for the new DCM. 6. Select Output file type and XST as Synthesis Tool.
11 Figure 11. Select the output file type and synthesis tool. 7. General Setup page. Provide input clock frequency 80MHz. This pins is driven by 80MHz clock generated in MainClock DCM. CLKIN Source is internal as this input clock is already buffered in MainClock DCM. Feedback Source is external for this DCM. This will be wired to BUS_SDRAM_FEEDBACK pin.
12 Figure 12. Configure Digital Clock Manager. 8. Select Use Global Buffers for all selected clock outputs option. This will insert Xilinx clock buffers in the output forcing place and route tool to place our clocks on dedicated global clock lines.
13 Figure 13. Enable Global Buffers for all output clocks. 9.Review all options and click on Finish button. This will produce our SdramBoardDeskew.vhd file which we can add to our design.
14 Figure 14. Review configuration and generate output files. NanoBoard 3000 Altera version 1. Launch the Altera MegaWizard Plug-In Manager. 2. Create a new custom megafunction variation.
15 Figure 15. Launching the Altera Megafunction Wizard. Click Next 2. Configure the MegaWizard Plug-In Manger for Cyclone III target. Browse to your project location and type in the output file name "SdramClocking" Select ALTPLL megafunction from the list.
16 Figure 16. Specifying the Megafunction Options. Click Next 3. Specify input clock frequency.
17 Figure 17. Setting the target clock frequency. Click Next 4. Enable 'areset' input port and 'locked' output port.
18 Figure 18. Enabling optional pins. Click Next 5. Accept default bandwidth settings and click Next.
19 Figure 19. Specifying Bandwidth settings. 6. Turn off Clock switchover option.
20 Figure 20. Clock switchover page. Click Next 7. Skip the Dynamic Configuration page.
21 Figure 21. Dynamic Configuration page. Click Next 8. Configure Wishbone Clock output port. Select 'Use this clock' option and specify input frequency 40 MHz.
22 Figure 22. Specifying the Wishbone Clock output. Click Next 9. Configure Memory Controller Sdram Clock. Enable C1 output and configure it for 80 MHz operation.
23 Figure 23. Specifying the Memory Controller Sdram Clock settings. Click Next 10. Configure Sdram Memory clock output port.
24 Figure 24. Specifying the Sdram Memory IC clock settings. Click Next 11. Skip C3 output page.
25 Figure 25. Skip unused clock output port page. Click Next 12. Ignore unused clock port.
26 Figure 26. Skip unused clock output port page. Click Next 13. Discard simulation library option.
27 Figure 27. Clik Next. 14. Click on Finish button and the MegaWizard Plug-in Manager will generate output files. Source URL:
SDRAM Interface Clocking for the NanoBoard 2
SDRAM Interface Clocking for the NanoBoard 2 NB2 + DB30 Xilinx Spartan 3 DaughterBoard 1. Schematic wiring for Xilinx DCM clocks. 2. Shared Memory Port Plugin wiring. NB2 + DB31 Altera Cyclone II DaughterBoard
Automatic Firmware Update Wizard
Automatic Firmware Update Wizard Frozen Content Modified by on 13-Sep-2017 Main article: NanoBoard 3000 - Firmware Updates The Automatic Firmware Update wizard. The Automatic Firmware Update wizard is used
EEC180B DIGITAL SYSTEMS Spring University of California, Davis. Department of Electrical and Computer Engineering
University of California, Davis Department of Electrical and Computer Engineering Tutorial: Instantiating and Using a PLL on the DE10 LITE Objective: This tutorial explains how to configure and instantiate
Configurable Generic Library
Configurable Generic Library Frozen Content Modified by on 13-Sep-2017 Altium Designer Winter 09 heralds the arrival of a new integrated library of configurable generic FPGA logic components FPGA Configurable
DKAN0011A Setting Up a Nios II System with SDRAM on the DE2
DKAN0011A Setting Up a Nios II System with SDRAM on the DE2 04 November 2009 Introduction This tutorial details how to set up and instantiate a Nios II system on Terasic Technologies, Inc. s DE2 Altera
White Paper Performing Equivalent Timing Analysis Between Altera Classic Timing Analyzer and Xilinx Trace
Introduction White Paper Between Altera Classic Timing Analyzer and Xilinx Trace Most hardware designers who are qualifying FPGA performance normally run bake-off -style software benchmark comparisons
Tutorial for Altera DE1 and Quartus II
Tutorial for Altera DE1 and Quartus II Qin-Zhong Ye December, 2013 This tutorial teaches you the basic steps to use Quartus II version 13.0 to program Altera s FPGA, Cyclone II EP2C20 on the Development
AltiumLive - Content Store
AltiumLive - Content Store Frozen Content Modified by on 13-Sep-2017 Introducing the AltiumLive Content Store. The Content Store is an area in AltiumLive dedicated to content - content that is invaluable
VIVADO TUTORIAL- TIMING AND POWER ANALYSIS
VIVADO TUTORIAL- TIMING AND POWER ANALYSIS IMPORTING THE PROJECT FROM ISE TO VIVADO Initially for migrating the same project which we did in ISE 14.7 to Vivado 2016.1 you will need to follow the steps
Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction
Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction UG-032405-6.0 User Guide This user guide describes the features and behavior of the ALTPLL_RECONFIG megafunction that you can configure
Implementing a Verilog design into the UWEE CPLD Development Board Using Xilinx s ISE 7.1i Software: A Tutorial
Implementing a Verilog design into the UWEE CPLD Development Board Using Xilinx s ISE 7.1i Software: A Tutorial Revision 0 By: Evan Gander Materials: The following are required in order to complete this
Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim. ver. 1.5
Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim ver. 1.5 1 Prepared by Marcin Rogawski, Ekawat (Ice) Homsirikamol, Kishore Kumar Surapathi and Dr. Kris Gaj The example codes used
EE 1315 DIGITAL LOGIC LAB EE Dept, UMD
EE 1315 DIGITAL LOGIC LAB EE Dept, UMD EXPERIMENT # 1: Logic building blocks The main objective of this experiment is to let you familiarize with the lab equipment and learn about the operation of the
DDR and DDR2 SDRAM Controller Compiler User Guide
DDR and DDR2 SDRAM Controller Compiler User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Operations Part Number Compiler Version: 8.1 Document Date: November 2008 Copyright 2008 Altera
Design Portability, Configurations and Constraints
Design Portability, Configurations and Constraints Summary This article describes what is required for design portability, and the role of configurations and constraints in achieving this portability.
Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim. ver. 1.3
Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim ver. 1.3 1 Prepared by Marcin Rogawski, Ekawat (Ice) Homsirikamol, Kishorekum Surapathi, and Dr. Kris Gaj The example codes used in
NIOS CPU Based Embedded Computer System on Programmable Chip
1 Objectives NIOS CPU Based Embedded Computer System on Programmable Chip EE8205: Embedded Computer Systems This lab has been constructed to introduce the development of dedicated embedded system based
and 32 bit for 32 bit. If you don t pay attention to this, there will be unexpected behavior in the ISE software and thing may not work properly!
This tutorial will show you how to: Part I: Set up a new project in ISE 14.7 Part II: Implement a function using Schematics Part III: Simulate the schematic circuit using ISim Part IV: Constraint, Synthesize,
WB_SDHC - Wishbone SDHC Controller
WB_SDHC - Wishbone SDHC Controller Frozen Content Modified by Admin on Sep 13, 2017 Parent article: FPGA Peripheral Components - Wishbone WB_SDHC - Wishbone SDHC Controller. The Wishbone SDHC Controller
AN 367: Implementing PLL Reconfiguration in Stratix II Devices
AN 367: Implementing PLL Reconfiguration in Stratix II Devices July 2012 AN-367-2.2 Introduction Phase-locked loops (PLLs) use several divide counters and different voltage-controlled oscillator (VCO)
Lab 3 Sequential Logic for Synthesis. FPGA Design Flow.
Lab 3 Sequential Logic for Synthesis. FPGA Design Flow. Task 1 Part 1 Develop a VHDL description of a Debouncer specified below. The following diagram shows the interface of the Debouncer. The following
Programming Xilinx SPARTAN 3 Board (Simulation through Implementation)
Programming Xilinx SPARTAN 3 Board (Simulation through Implementation) September 2008 Prepared by: Oluwayomi Adamo Class: Project IV University of North Texas FPGA Physical Description 4 1. VGA (HD-15)
High-Performance FPGA PLL Analysis with TimeQuest
High-Performance FPGA PLL Analysis with TimeQuest August 2007, ver. 1.0 Application Note 471 Introduction f Phase-locked loops (PLLs) provide robust clock management and clock synthesis capabilities for
Xilinx ISE8.1 and Spartan-3 Tutorial EE3810
Xilinx ISE8.1 and Spartan-3 Tutorial EE3810 1 Part1) Starting a new project Simple 3-to-8 Decoder Start the Xilinx ISE 8.1i Project Navigator: Select File > New Project in the opened window 2 Select a
Lab 1: Introduction to Verilog HDL and the Xilinx ISE
EE 231-1 - Fall 2016 Lab 1: Introduction to Verilog HDL and the Xilinx ISE Introduction In this lab simple circuits will be designed by programming the field-programmable gate array (FPGA). At the end
Tutorial on FPGA Design Flow based on Aldec Active HDL. Ver 1.5
Tutorial on FPGA Design Flow based on Aldec Active HDL Ver 1.5 1 Prepared by Ekawat (Ice) Homsirikamol, Marcin Rogawski, Jeremy Kelly, Kishore Kumar Surapathi and Dr. Kris Gaj This tutorial assumes that
1. Downloading. 2. Installation and License Acquiring. Xilinx ISE Webpack + Project Setup Instructions
Xilinx ISE Webpack + Project Setup Instructions 1. Downloading The Xilinx tools are free for download from their website and can be installed on your Windowsbased PC s. Go to the following URL: http://www.xilinx.com/support/download/index.htm
SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide
SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: 8.1 Document Version: 4.0 Document Date: November 2008 UG-MF9504-4.0
altpll Megafunction User Guide 101 Innovation Drive San Jose, CA (408)
altpll Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Quartus II Version: 2.2 Document Version: 2.0 Document Date: February 2003 Copyright altpll Megafunction
Circuit design with configurable devices (FPGA)
1 Material Circuit design with configurable devices (FPGA) Computer with Xilinx's ISE software installed. Digilent's Basys2 prototype board and documentation. Sample design files (lab kit). Files and documents
My First FPGA for Altera DE2-115 Board
My First FPGA for Altera DE2-115 Board 數位電路實驗 TA: 吳柏辰 Author: Trumen Outline Complete Your Verilog Design Assign The Device Add a PLL Megafunction Assign the Pins Create a Default TimeQuest SDC File Compile
Tutorial on FPGA Design Flow based on Xilinx ISE WebPack and ModelSim. ver. 2.0
Tutorial on FPGA Design Flow based on Xilinx ISE WebPack and ModelSim ver. 2.0 Updated: Fall 2013 1 Preparing the Input: Download examples associated with this tutorial posted at http://ece.gmu.edu/tutorials-and-lab-manuals
Tutorial on FPGA Design Flow based on Aldec Active HDL. Ver 1.5
Tutorial on FPGA Design Flow based on Aldec Active HDL Ver 1.5 1 Prepared by Ekawat (Ice) Homsirikamol, Marcin Rogawski, Jeremy Kelly, John Pham, and Dr. Kris Gaj This tutorial assumes that you have basic
Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 11/01/17
1 Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 11/01/17 The following is a general outline of steps (i.e. design flow) used to implement a digital system described with
ECE 4305 Computer Architecture Lab #1
ECE 4305 Computer Architecture Lab #1 The objective of this lab is for students to familiarize with the FPGA prototyping system board (Nexys-2) and the Xilinx software development environment that will
Xilinx ISE Synthesis Tutorial
Xilinx ISE Synthesis Tutorial The following tutorial provides a basic description of how to use Xilinx ISE to create a simple 2-input AND gate and synthesize the design onto the Spartan-3E Starter Board
2. SDRAM Controller Core
2. SDRAM Controller Core Core Overview The SDRAM controller core with Avalon interface provides an Avalon Memory-Mapped (Avalon-MM) interface to off-chip SDRAM. The SDRAM controller allows designers to
CHAPTER 1 INTRODUCTION... 1 CHAPTER 2 ASSIGN THE DEVICE... 7 CHAPTER 3 DESIGN ENTRY CHAPTER 4 COMPILE AND VERIFY YOUR DESIGN...
CONTENTS CHAPTER 1 INTRODUCTION... 1 1.1 DESIGN FLOW... 1 1.2 BEFORE YOU BEGIN... 2 1.3 WHAT YOU WILL LEARN... 6 CHAPTER 2 ASSIGN THE DEVICE... 7 2.1 ASSIGN THE DEVICE... 7 CHAPTER 3 DESIGN ENTRY... 11
Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 10/25/16
1 Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 10/25/16 The following is a general outline of steps (i.e. design flow) used to implement a digital system described with
Defining Net Classes by Area on a Schematic. Creating a Net Class from a Blanket Directive. Modified by Admin on Sep 13, Blankets in Schematic
Defining Net Classes by Area on a Schematic Old Content - visit altium.com/documentation Modified by Admin on Sep 13, 2017 Related Video Blankets in Schematic Altium Designer already allows you to create
8. Migrating Stratix II Device Resources to HardCopy II Devices
8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.3 Introduction Altera HardCopy II devices and Stratix II devices are both manufactured on a 1.2-V, 90-nm process technology and
DE2 Board & Quartus II Software
January 23, 2015 Contact and Office Hours Teaching Assistant (TA) Sergio Contreras Office Office Hours Email SEB 3259 Tuesday & Thursday 12:30-2:00 PM Wednesday 1:30-3:30 PM contre47@nevada.unlv.edu Syllabus
Lab 3: Xilinx PicoBlaze Flow Lab Targeting Spartan-3E Starter Kit
Lab 3: Xilinx PicoBlaze Flow Lab Targeting Spartan-3E Starter Kit Xilinx PicoBlaze Flow Demo Lab www.xilinx.com 1-1 Create a New Project Step 1 Create a new project targeting the Spartan-3E device that
Xilinx ISE8.1 and Spartan-3 Tutorial (Prepared by Kahraman Akdemir based on Professor Duckworth's Tutorials updated September 2006)
Xilinx ISE8.1 and Spartan-3 Tutorial (Prepared by Kahraman Akdemir based on Professor Duckworth's Tutorials updated September 2006) 1 Part1) Starting a new project Simple 3-to-8 Decoder Start the Xilinx
Stratix FPGA Family. Table 1 shows these issues and which Stratix devices each issue affects. Table 1. Stratix Family Issues (Part 1 of 2)
January 2007, ver. 3.1 Errata Sheet This errata sheet provides updated information on Stratix devices. This document addresses known issues and includes methods to work around the issues. Table 1 shows
Tutorial on FPGA Design Flow based on Xilinx ISE Webpack andisim. ver. 1.0
Tutorial on FPGA Design Flow based on Xilinx ISE Webpack andisim ver. 1.0 1 Prepared by Malik Umar Sharif and Dr. Kris Gaj The example codes used in this tutorial can be obtained from http://ece.gmu.edu/coursewebpages/ece/ece448/s11/labs/448_lab3.htm
1. SDRAM Controller Core
1. SDRAM Controller Core NII51005-7.2.0 Core Overview The SDRAM controller core with Avalon interface provides an Avalon Memory-Mapped (Avalon-MM) interface to off-chip SDRAM. The SDRAM controller allows
ECE 491 Laboratory 1 Introducing FPGA Design with Verilog September 6, 2004
Goals ECE 491 Laboratory 1 Introducing FPGA Design with Verilog September 6, 2004 1. To review the use of Verilog for combinational logic design. 2. To become familiar with using the Xilinx ISE software
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
Clock Control Block (ALTCLKCTRL) Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Document Version: 2.4 Document Date: December 2008 Copyright 2008 Altera Corporation. All
FPGA. Logic Block. Plessey FPGA: basic building block here is 2-input NAND gate which is connected to each other to implement desired function.
FPGA Logic block of an FPGA can be configured in such a way that it can provide functionality as simple as that of transistor or as complex as that of a microprocessor. It can used to implement different
High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example User Guide
High Bandwidth Memory (HBM2) Interface Intel FPGA IP Design Example Updated for Intel Quartus Prime Design Suite: 18.1.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. High Bandwidth
NanoBoard Configuring an FPGA Project Automatically. Identifying System Hardware. Modified by Admin on Sep 13, 2017
NanoBoard 3000 - Configuring an FPGA Project Automatically Frozen Content Modified by Admin on Sep 13, 2017 Parent article: Understanding the NanoBoard 3000 Constraint System Although an FPGA design project
Graduate Institute of Electronics Engineering, NTU. FPGA Lab. Speaker : 鍾明翰 (CMH) Advisor: Prof. An-Yeu Wu Date: 2010/12/14 ACCESS IC LAB
FPGA Lab Speaker : 鍾明翰 (CMH) Advisor: Prof. An-Yeu Wu Date: 2010/12/14 ACCESS IC LAB Objective In this Lab, you will learn the basic set-up and design methods of implementing your design by ISE 10.1. Create
NanoBoard MIDI Interface
NanoBoard 3000 - MIDI Interface Frozen Content Mod ifi ed by Adm in on Nov 6, 201 3 The NanoBoard 3000 caters for transmission and reception of signals in accordance with the MIDI (Musical Instrument Digital
ALTERA FPGAs Architecture & Design
ALTERA FPGAs Architecture & Design Course Description This course provides all theoretical and practical know-how to design programmable devices of ALTERA with QUARTUS-II design software. The course combines
Field Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA) Lecturer: Krébesz, Tamas 1 FPGA in general Reprogrammable Si chip Invented in 1985 by Ross Freeman (Xilinx inc.) Combines the advantages of ASIC and uc-based systems
Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide
Error Correction Code (ALTECC_ENCODER and ALTECC_DECODER) Megafunctions User Guide 11 Innovation Drive San Jose, CA 95134 www.altera.com Software Version 8. Document Version: 2. Document Date: June 28
Intel MAX 10 Clocking and PLL User Guide
Intel MAX 10 Clocking and PLL User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Intel MAX 10 Clocking and PLL
ISE Simulator (ISim) In-Depth Tutorial. UG682 (v 13.1) March 1, 2011
ISE Simulator (ISim) In-Depth Tutorial Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate
Building Combinatorial Circuit Using Behavioral Modeling Lab
Building Combinatorial Circuit Using Behavioral Modeling Lab Overview: In this lab you will learn how to model a combinatorial circuit using behavioral modeling style of Verilog HDL. You will model a combinatorial
Intel MAX 10 Clocking and PLL User Guide
Intel MAX 10 Clocking and PLL User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1 Intel MAX 10 Clocking and PLL
Physics 536 Spring Illustrating the FPGA design process using Quartus II design software and the Cyclone II FPGA Starter Board.
Physics 536 Spring 2009 Illustrating the FPGA design process using Quartus II design software and the Cyclone II FPGA Starter Board. Digital logic: Equivalent to a large number of discrete logic elements
Component Management in SOLIDWORKS PCB
Component Management in SOLIDWORKS PCB Modified by Jason Howie on Oct 24, 2017 Parent page: Exploring SOLIDWORKS PCB A component is the general name given to a part that can be placed into an electronic
Tutorial on FPGA Design Flow based on Aldec Active HDL. ver 1.7
Tutorial on FPGA Design Flow based on Aldec Active HDL ver 1.7 Fall 2012 1 Prepared by Ekawat (Ice) Homsirikamol, Marcin Rogawski, Jeremy Kelly, Kishore Kumar Surapathi, Ambarish Vyas, Malik Umar Sharif
INTRODUCTION TO FPGA ARCHITECTURE
3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)
5. Clock Networks and PLLs in Stratix IV Devices
September 2012 SIV51005-3.4 5. Clock Networks and PLLs in Stratix IV Devices SIV51005-3.4 This chapter describes the hierarchical clock networks and phase-locked loops (PLLs) which have advanced features
SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide
SERDES Transmitter/Receiver (ALTLVDS) Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: 7.2 Document Version: 3.3 Document Date: November 2007 Copyright 2007
Implementation of a Fail-Safe Design in the Spartan-6 Family Using ISE Design Suite XAPP1104 (v1.0.1) June 19, 2013
Implementation of a Fail-Safe Design in the Spartan-6 Family Using ISE Design Suite 12.4 Notice of Disclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection
Published on Online Documentation for Altium Products (
Published on Online Documentation for Altium Products (https://www.altium.com/documentation) Home > Schematic Symbol Generation Tool Using Altium Documentation Modified by Jason Howie on Apr 11, 2017 Parent
IDEA! Avnet SpeedWay Design Workshop
The essence of FPGA technology IDEA! 2 ISE Tool Flow Overview Design Entry Synthesis Constraints Synthesis Simulation Implementation Constraints Floor-Planning Translate Map Place & Route Timing Analysis
CHAPTER 1 Introduction of the tnano Board CHAPTER 2 tnano Board Architecture CHAPTER 3 Using the tnano Board... 8
CONTENTS CHAPTER 1 Introduction of the tnano Board... 2 1.1 Features...2 1.2 About the KIT...4 1.3 Getting Help...4 CHAPTER 2 tnano Board Architecture... 5 2.1 Layout and Components...5 2.2 Block Diagram
Design Flow Tutorial
Digital Design LU Design Flow Tutorial Jakob Lechner, Thomas Polzer {lechner, tpolzer}@ecs.tuwien.ac.at Department of Computer Engineering University of Technology Vienna Vienna, October 8, 2010 Contents
Reduce Your System Power Consumption with Altera FPGAs Altera Corporation Public
Reduce Your System Power Consumption with Altera FPGAs Agenda Benefits of lower power in systems Stratix III power technology Cyclone III power Quartus II power optimization and estimation tools Summary
Tutorial - Using Xilinx System Generator 14.6 for Co-Simulation on Digilent NEXYS3 (Spartan-6) Board
Tutorial - Using Xilinx System Generator 14.6 for Co-Simulation on Digilent NEXYS3 (Spartan-6) Board Shawki Areibi August 15, 2017 1 Introduction Xilinx System Generator provides a set of Simulink blocks
Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
2015.05.04 Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide UG-01155 Subscribe The Altera IOPLL megafunction IP core allows you to configure the settings of Arria 10 I/O PLL. Altera IOPLL
ELEC 204 Digital System Design LABORATORY MANUAL
ELEC 204 Digital System Design LABORATORY MANUAL : Introductory Tutorial For Xilinx ISE Foundation v10.1 & Implementing XOR Gate College of Engineering Koç University Important Note: In order to effectively
Section I. Cyclone II Device Family Data Sheet
Section I. Cyclone II Device Family Data Sheet This section provides information for board layout designers to successfully layout their boards for Cyclone II devices. It contains the required PCB layout
Intel Stratix 10 H-tile Hard IP for Ethernet Design Example User Guide
Intel Stratix 10 H-tile Hard IP for Ethernet Design Example User Guide Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
Getting started with the Xilinx Project Navigator and the Digilent BASYS 2 board.
Getting started with the Xilinx Project Navigator and the Digilent BASYS 2 board. This lab is based on: Xilinx Project Navigator, Release Version 14.6 Digilent Adept System Rev 2.7, Runtime Rev 2.16 Digilent
altshift_taps Megafunction User Guide
altshift_taps Megafunction User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Document Version: 1.0 Document Date: September 2004 Copyright 2004 Altera Corporation. All rights
Spartan-6 FPGA Clocking Resources
Spartan-6 FPGA Clocking Resources User Guide Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to
FPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011
FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level
AccelDSP tutorial 2 (Matlab.m to HDL for Xilinx) Ronak Gandhi Syracuse University Fall
AccelDSP tutorial 2 (Matlab.m to HDL for Xilinx) Ronak Gandhi Syracuse University Fall 2009-10 AccelDSP Getting Started Tutorial Introduction This tutorial exercise will guide you through the process of
Core Facts. Documentation Design File Formats. Verification Instantiation Templates Reference Designs & Application Notes Additional Items
(FFT_MIXED) November 26, 2008 Product Specification Dillon Engineering, Inc. 4974 Lincoln Drive Edina, MN USA, 55436 Phone: 952.836.2413 Fax: 952.927.6514 E mail: info@dilloneng.com URL: www.dilloneng.com
ISE In-Depth Tutorial. UG695 (v13.1) March 1, 2011
ISE In-Depth Tutorial The information disclosed to you hereunder (the Information ) is provided AS-IS with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from
Implementing PLL Reconfiguration in Stratix & Stratix GX Devices
December 2005, ver. 2.0 Implementing PLL Reconfiguration in Stratix & Stratix GX Devices Application Note 282 Introduction Phase-locked loops (PLLs) use several divide counters and delay elements to perform
Published on Online Documentation for Altium Products (
Published on Online Documentation for Altium Products (https://www.altium.com/documentation) Home > PCB - From-To Editor Using Altium Documentation Modified by Admin on Apr 11, 2017 Parent page: PCB Panels
Altera Technical Training Quartus II Software Design
Altera Technical Training Quartus II Software Design Exercises Quartus II Software Design Series: Foundation 2 Quartus II Software Design Series: Foundation Exercises Exercise 1 3 Exercises Quartus II
Xilinx Tutorial Basic Walk-through
Introduction to Digital Logic Design with FPGA s: Digital logic circuits form the basis of all digital electronic devices. FPGAs (Field Programmable Gate Array) are large programmable digital electronic
3. ALTGX_RECONFIG IP Core User Guide for Stratix IV Devices
July 2014 SIV53004-2014.07.09 3. ALTGX_RECONFIG IP Core User Guide for Stratix IV Devices SIV53004-2014.07.09 This document describes how to define and instantiate the ALTGX_RECONFIG IP core using the
DDR & DDR2 SDRAM Controller Compiler
DDR & DDR2 SDRAM Controller Compiler November 2005, Compiler Version 3.2.0 Errata Sheet Introduction This document addresses known errata and documentation changes for version 3.2.0 of the DDR & DDR2 SDRAM
Tutorial: ISE 12.2 and the Spartan3e Board v August 2010
Tutorial: ISE 12.2 and the Spartan3e Board v12.2.1 August 2010 This tutorial will show you how to: Use a combination of schematics and Verilog to specify a design Simulate that design Define pin constraints
Graphical Display of Power Monitoring Data
Graphical Display of Power Monitoring Data Frozen Content Modified by on 6-Nov-2013 Display of power monitoring information in tabular format is good, but a visual representation of the values over time
Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction
Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction May 2008, v.1.2 Introduction Application Note 462 Many systems and applications use external memory interfaces as data storage or
Virtex-II SiberBridge Author: Ratima Kataria & the SiberCore Applications Engineering Group
Application Note: Virtex-II Family XAPP254 (v1.1) February 25, 2005 R Author: Ratima Kataria & the SiberCore Applications Engineering Group Summary Designed to be implemented in a Virtex -II FPGA, the
Verilog Design Entry, Synthesis, and Behavioral Simulation
------------------------------------------------------------- PURPOSE - This lab will present a brief overview of a typical design flow and then will start to walk you through some typical tasks and familiarize
Field Programmable Gate Array (FPGA) Devices
Field Programmable Gate Array (FPGA) Devices 1 Contents Altera FPGAs and CPLDs CPLDs FPGAs with embedded processors ACEX FPGAs Cyclone I,II FPGAs APEX FPGAs Stratix FPGAs Stratix II,III FPGAs Xilinx FPGAs
University of Hawaii EE 361L. Getting Started with Spartan 3E Digilent Basys2 Board. Lab 4.1
University of Hawaii EE 361L Getting Started with Spartan 3E Digilent Basys2 Board Lab 4.1 I. Test Basys2 Board Attach the Basys2 board to the PC or laptop with the USB connector. Make sure the blue jumper
Spartan -6 LX150T Development Kit Hardware Co-Simulation Reference Design User Guide
Spartan -6 LX150T Development Kit H/W Co-Simulation Reference Design User Guide Spartan -6 LX150T Development Kit Hardware Co-Simulation Reference Design User Guide Version 0.8 Revision History Version
9. Building Memory Subsystems Using SOPC Builder
9. Building Memory Subsystems Using SOPC Builder QII54006-6.0.0 Introduction Most systems generated with SOPC Builder require memory. For example, embedded processor systems require memory for software