Lecture 6. Advanced Testbenches. George Mason University
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1 Lecture 6 Advanced Testbenches George Mason University
2 Required reading Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 14, starting from Design Verification 2
3 Steps of the Design Process 1. Text description 2. Interface 3. Pseudocode 4. Block diagram of the Datapath 5. Interface with the division into the Datapath and the Controller 6. ASM chart of the Controller 7. RTL VHDL code of the Datapath, the Controller, and the Top Unit 8. Testbench of the Datapath, the Controller, and the Top Unit 9. Functional simulation and debugging 10. Synthesis and post-synthesis simulation 11. Implementation and timing simulation 12. Experimental testing 3
4 Advanced Testbench (1) Processes Generating Input Stimuli Design Under Test (DUT) Process Comparing Actual Outputs vs. Expected Outputs Yes/No Design Correct/Incorrect 4
5 Advanced Testbench (2) Processes Generating Input Stimuli Design Under Test (DUT) Process Comparing Actual Outputs vs. Expected Outputs Testvector file(s) Yes/No Design Correct/Incorrect 5
6 Asserts & Reports ECE 448 FPGA and ASIC Design with VHDL 6
7 Assert Assert is a non-synthesizable statement whose purpose is to write out messages on the screen when problems are found during simulation. Depending on the severity of the problem, The simulator is instructed to continue simulation or halt. 7
8 Assert - syntax ASSERT condition [REPORT "message ] [SEVERITY severity_level ]; The message is written when the condition is FALSE. Severity_level can be: Note, Warning, Error (default), or Failure. 8
9 Assert Examples (1) assert initial_value <= max_value report "initial value too large" severity error; assert packet_length /= 0 report "empty network packet received" severity warning; assert false report "Initialization complete" severity note; 9
10 Assert Examples (2) stim_proc: process begin wait for 20 ns assert false report "PASSED CHECKPOINT 1" severity note; wait for 10 ns; assert false report "PASSED CHECKPOINT 2" severity warning; 10
11 Assert Examples (3) end process; wait for 10 ns; assert false report "PASSED CHECKPOINT 3" severity error; wait for 10 ns; assert false report "PASSED CHECKPOINT 4" severity failure; wait; ECE 448 FPGA and ASIC Design with VHDL 11
12 Format of messages in Aldec Active-HDL 12
13 Format of messages in Xilinx ISim 13
14 Report - syntax REPORT "message" [SEVERITY severity_level ]; The message is always written. Severity_level can be: Note (default), Warning, Error, or Failure. 14
15 Report - Examples report "Initialization complete"; report "Current time = " & time'image(now); report "Incorrect branch" severity error; 15
16 Report - Examples library IEEE; use IEEE.STD_LOGIC_1164.all; entity example_1_tb is end example_1_tb; architecture behavioral of example_1_tb is signal clk : std_logic := '0'; begin clk <= not clk after 100 ns; process begin wait for 1000 ns; report "Initialization complete"; report "Current time = " & time'image(now); wait for 1000 ns; report "SIMULATION COMPLETED" severity failure; end process; end behavioral; 16
17 Advanced Testbench (1) Processes Generating Input Stimuli Design Under Test (DUT) Process Comparing Actual Outputs vs. Expected Outputs Yes/No Design Correct/Incorrect 17
18 Records ECE 448 FPGA and ASIC Design with VHDL 18
19 Records TYPE test_vector IS RECORD operation : STD_LOGIC_VECTOR(1 DOWNTO 0); a : STD_LOGIC; b: STD_LOGIC; y : STD_LOGIC; END RECORD; CONSTANT num_vectors : INTEGER := 16; TYPE test_vectors IS ARRAY (0 TO num_vectors-1) OF test_vector; CONSTANT and_op : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; CONSTANT or_op : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; CONSTANT xor_op : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; CONSTANT xnor_op : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; 19
20 Records CONSTANT test_vector_table: test_vectors :=( (operation => AND_OP, a=>'0', b=>'0', y=>'0'), (operation => AND_OP, a=>'0', b=>'1', y=>'0'), (operation => AND_OP, a=>'1', b=>'0', y=>'0'), (operation => AND_OP, a=>'1', b=>'1', y=>'1'), (operation => OR_OP, a=>'0', b=>'0', y=>'0'), (operation => OR_OP, a=>'0', b=>'1', y=>'1'), (operation => OR_OP, a=>'1', b=>'0', y=>'1'), (operation => OR_OP, a=>'1', b=>'1', y=>'1'), (operation => XOR_OP, a=>'0', b=>'0', y=>'0'), (operation => XOR_OP, a=>'0', b=>'1', y=>'1'), (operation => XOR_OP, a=>'1', b=>'0', y=>'1'), (operation => XOR_OP, a=>'1', b=>'1', y=>'0'), (operation => XNOR_OP, a=>'0', b=>'0', y=>'1'), (operation => XNOR_OP, a=>'0', b=>'1', y=>'0'), (operation => XNOR_OP, a=>'1', b=>'0', y=>'0'), (operation => XNOR_OP, a=>'1', b=>'1', y=>'1') ); 20
21 Variables ECE 448 FPGA and ASIC Design with VHDL 21
22 Variables - features Can only be declared within processes and subprograms (functions & procedures) Initial value can be explicitly specified in the declaration When assigned take an assigned value immediately Variable assignments represent the desired behavior, not the structure of the circuit Can be used freely in testbenches Should be avoided, or at least used with caution in a synthesizable code 22
23 Variables - Example testing: PROCESS VARIABLE error_cnt: INTEGER := 0; BEGIN FOR i IN 0 to num_vectors-1 LOOP test_operation <= test_vector_table(i).operation; test_a <= test_vector_table(i).a; test_b <= test_vector_table(i).b; WAIT FOR 10 ns; IF test_y /= test_vector_table(i).y THEN error_cnt := error_cnt + 1; END IF; END LOOP; END PROCESS testing; 23
24 Using Arrays of Test Vectors In Testbenches ECE 448 FPGA and ASIC Design with VHDL 24
25 Testbench (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY sevensegmenttb IS END sevensegmenttb; ARCHITECTURE testbench OF sevensegmenttb IS COMPONENTsevenSegment PORT ( bcdinputs : IN STD_LOGIC_VECTOR (3 DOWNTO 0); seven_seg_outputs : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); ); end COMPONENT; CONSTANT PropDelay: time := 40 ns; CONSTANT SimLoopDelay: time := 10 ns; 25
26 Testbench (2) TYPE vector IS RECORD bcdstimulus: STD_LOGIC_VECTOR(3 DOWNTO 0); sevsegout: STD_LOGIC_VECTOR(6 DOWNTO 0); END RECORD; CONSTANT NumVectors: INTEGER:= 10; TYPE vectorarray is ARRAY (0 TO NumVectors - 1) OF vector; CONSTANT vectortable: vectorarray := ( (bcdstimulus => "0000", sevsegout => " "), (bcdstimulus => "0001", sevsegout => " "), (bcdstimulus => "0010", sevsegout => " "), (bcdstimulus => "0011", sevsegout => " "), (bcdstimulus => "0100", sevsegout => " "), (bcdstimulus => "0101", sevsegout => " "), (bcdstimulus => "0110", sevsegout => " "), (bcdstimulus => "0111", sevsegout => " "), (bcdstimulus => "1000", sevsegout => " "), (bcdstimulus => "1001", sevsegout => " ") ); 26
27 Testbench (3) SIGNAL StimInputs: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CaptureOutputs: STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN u1: sevensegment PORT MAP ( bcdinputs => StimInputs, seven_seg_outputs => CaptureOutputs); 27
28 Testbench (4) LoopStim: PROCESS BEGIN FOR i in 0 TO NumVectors-1 LOOP StimInputs <= vectortable(i).bcdstimulus; WAIT FOR PropDelay; ASSERT CaptureOutputs == vectortable(i).sevsegout REPORT Incorrect Output SEVERITY error; WAIT FOR SimLoopDelay; Verify outputs! END LOOP; 28
29 Testbench (5) WAIT; END PROCESS; END testbench; 29
30 Advanced Testbench (2) Processes Generating Input Stimuli Design Under Test (DUT) Process Comparing Actual Outputs vs. Expected Outputs Testvector file(s) Yes/No Design Correct/Incorrect 30
31 File I/O ECE 448 FPGA and ASIC Design with VHDL 31
32 File I/O Example Example of file input/output using a counter Text file is vectorfile.txt Has both input data and EXPECTED output data Will compare VHDL output data with EXPECTED output data! 32
33 Design Under Test (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY loadcnt IS PORT ( data: IN STD_LOGIC_VECTOR (7 DOWNTO 0); load: IN STD_LOGIC; clk: IN STD_LOGIC; rst: IN STD_LOGIC; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END loadcnt; 33
34 Design Under Test (2) ARCHITECTURE rtl OF loadcnt IS SIGNAL cnt: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN counter: PROCESS (clk, rst) BEGIN IF (rst = '1') THEN cnt <= (OTHERS => '0'); ELSIF (clk'event AND clk = '1') THEN IF (load = '1') THEN cnt <= data; ELSE cnt <= cnt + 1; END IF; END IF; END PROCESS; q <= cnt; END rtl; 34
35 Test vector file (1) #Format is Rst, Load, Data, Q #load the counter to all 1s #reset the counter #now perform load/increment for each bit # # #
36 Test vector file (2) # # # # # #check roll-over case # # End vectors 36
37 Methodology to test vectors from file Verify output is as expected: compare Qout (the output of the VHDL counter) with Qexpected (the expected value of Q from the test file) clk read vector from text file into variables (vrst, vload, vdata, vq) Apply input data to counter (i.e. rst <= vrst, load <= vload, reset <=vreset, data <= vdata) 37
38 Testbench (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_textio.all; LIBRARY std; USE std.textio.all; ENTITY loadcnttb IS END loadcnttb; ARCHITECTURE testbench OF loadcnttb IS COMPONENT loadcnt PORT ( data: IN STD_LOGIC_VECTOR (7 DOWNTO 0); load: IN STD_LOGIC; clk: IN STD_LOGIC; rst: IN STD_LOGIC; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; 38
39 Testbench (2) FILE vectorfile: TEXT OPEN READ_MODE is "vectorfile.txt"; SIGNAL Data: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL Load: STD_LOGIC; SIGNAL Rst: STD_LOGIC; SIGNAL Qout: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL Qexpected: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL TestClk: CONSTANT ClkPeriod: BEGIN STD_LOGIC := '0'; TIME := 100 ns; -- Free running test clock TestClk <= NOT TestClk AFTER ClkPeriod/2; -- Instance of design being tested u1: loadcnt PORT MAP (Data => Data, load => Load, clk => TestClk, rst => Rst, q => Qout ); 39
40 Testbench (4) -- File reading and stimulus application readvec: PROCESS VARIABLE VectorLine: LINE; VARIABLE VectorValid: BOOLEAN; VARIABLE vrst: STD_LOGIC; VARIABLE vload: STD_LOGIC; VARIABLE vdata: STD_LOGIC_VECTOR(7 DOWNTO 0); VARIABLE vq: STD_LOGIC_VECTOR(7 DOWNTO 0); VARIABLE space: CHARACTER; 40
41 Testbench (5) BEGIN WHILE NOT ENDFILE (vectorfile) LOOP readline(vectorfile, VectorLine); -- put file data into line read(vectorline, vrst, good => VectorValid); NEXT WHEN NOT VectorValid; read(vectorline, space); read(vectorline, vload); read(vectorline, space); read(vectorline, vdata); read(vectorline, space); read(vectorline, vq); WAIT FOR ClkPeriod/4; Rst <= vrst; Load <= vload; Data <= vdata; Qexpected <= vq; WAIT FOR (ClkPeriod/4) * 3; END LOOP; 41
42 Testbench (6) ASSERT FALSE REPORT "Simulation complete" SEVERITY NOTE; WAIT; END PROCESS; -- Process to verify outputs verify: PROCESS (TestClk) variable ErrorMsg: LINE; BEGIN IF (TestClk'event AND TestClk = '0') THEN IF Qout /= Qexpected THEN write(errormsg, STRING'("Vector failed ")); write(errormsg, now); writeline(output, ErrorMsg); END IF; END IF; END PROCESS; END testbench; 42
43 Simulation Waveform Verify output is as expected: compare Q (the output of the VHDL counter) with Qexpected (the expected value of Q from the test file) read vector from text file into variables (vrst, vload, vdata, vq) Apply input data to counter (i.e. rst <= vrst, load <= vload, reset <=vreset, data <= vdata) 43
44 Hex format In order to read/write data in the hexadecimal notation, replace read with hread, and write with hwrite 44
45 Note on test file This example showed a test file that had both the control commands (i.e. load, reset), and the actual data itself Often the test file just has the input and output vectors (and no load, reset, etc.) 45
46 ? 46
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