ECE 545 Lecture 7. Modeling of Circuits with a Regular Structure. Aliases, Attributes, Packages. Mixing Design Styles. George Mason University
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1 ECE 545 Lecture 7 Modeling of Circuits with a Regular Structure Aliases, Attributes, Packages Mixing Design Styles George Mason University
2 Required reading P. Chu, RTL Hardware Design using VHDL Chapters 14.5 For Generate Statement 14.6 Conditional Generate Statement 15.2 Data Types for Two-Dimensional Signals 15.3 Commonly Used Intermediate-Sized RT-Level Components 2
3 Generate scheme for equations ECE 448 FPGA and ASIC Design with VHDL 3
4 Dataflow VHDL Major instructions Concurrent statements concurrent signal assignment ( ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) 4
5 PARITY Example 5
6 PARITY: Block Diagram 6
7 PARITY: Entity Declaration LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC ); END parity; 7
8 PARITY: Block Diagram xor_out(1) xor_out(2) xor_out(3) xor_out(4) xor_out(5) xor_out(6) 8
9 PARITY: Architecture ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: std_logic_vector (6 downto 1); BEGIN xor_out(1) <= parity_in(0) XOR parity_in(1); xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); parity_out <= xor_out(6) XOR parity_in(7); END parity_dataflow; 9
10 PARITY: Architecture (2) ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (6 DOWNTO 1); BEGIN G2: FOR i IN 1 TO 7 GENERATE left_xor: IF i=1 GENERATE xor_out(i) <= parity_in(i-1) XOR parity_in(i); END GENERATE; middle_xor: IF (i >1) AND (i<7) GENERATE xor_out(i) <= xor_out(i-1) XOR parity_in(i); END GENERATE; right_xor: IF i=7 GENERATE parity_out <= xor_out(i-1) XOR parity_in(i); END GENERATE; END GENERATE; END parity_dataflow; 10
11 PARITY: Block Diagram (2) xor_out(0) xor_out(1) xor_out(2) xor_out(3) xor_out(4) xor_out(5) xor_out(6) xor_out(7) 11
12 PARITY: Architecture ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 downto 0); BEGIN xor_out(0) <= parity_in(0); xor_out(1) <= xor_out(0) XOR parity_in(1); xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); xor_out(7) <= xor_out(6) XOR parity_in(7); parity_out <= xor_out(7); END parity_dataflow; 12
13 PARITY: Architecture (2) ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN xor_out(0) <= parity_in(0); G2: FOR i IN 1 TO 7 GENERATE xor_out(i) <= xor_out(i-1) XOR parity_in(i); END GENERATE G2; parity_out <= xor_out(7); END parity_dataflow; 13
14 For Generate Statement For - Generate label: FOR identifier IN range GENERATE {Concurrent Statements} END GENERATE; 14
15 Conditional Generate Statement If - Generate label: IF boolean_expression GENERATE {Concurrent Statements} END GENERATE; 15
16 Generate scheme for components ECE 448 FPGA and ASIC Design with VHDL 16
17 Structural VHDL Major instructions component instantiation (port map) component instantiation with generic (generic map, port map) generate scheme for component instantiations (for-generate) 17
18 Example 1 18
19 Example 1 s 0 s 1 w 0 w 3 w 4 s 2 s 3 w 7 f w 8 w 11 w 12 w 15 19
20 A 4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE Dataflow OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Dataflow ; 20
21 Straightforward code for Example 1 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Example1 IS PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ; s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END Example1 ; 21
22 Straightforward code for Example 1 ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ; Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ; Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ; Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ; 22
23 Modified code for Example 1 ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; END COMPONENT ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Muxes: mux4to1 PORT MAP ( w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ; END GENERATE ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ; 23
24 Example 2 24
25 Example 2 w 1 w 1 y 3 y 15 w 0 w 0 y 2 y 14 y 1 y 13 En y 0 y 12 w 3 w 2 w 1 y 3 w 0 y 2 w 1 y 3 w 0 y 2 En y 1 y 0 y 11 y 10 y 9 y 8 En En y 1 y 0 w 1 y 3 w 0 y 2 En y 1 y 0 y 7 y 6 y 5 y 4 w 1 y 3 w 0 y 2 En y 1 y 0 y 3 y 2 y 1 y 0 25
26 A 2-to-4 binary decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END dec2to4 ; ARCHITECTURE Dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "0001" WHEN "100", "0010" WHEN "101", "0100" WHEN "110", 1000" WHEN "111", "0000" WHEN OTHERS ; END Dataflow ; 26
27 VHDL code for Example 2 (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec4to16 IS PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END dec4to16 ; 27
28 VHDL code for Example 2 (2) ARCHITECTURE Structure OF dec4to16 IS COMPONENT dec2to4 PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(3 DOWNTO 0) ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i+3 DOWNTO 4*i) ); END GENERATE ; Dec_left: dec2to4 PORT MAP ( w(3 DOWNTO 2), En, m ) ; END Structure ; 28
29 Example 3 Up-or-down Free Running Counter 29
30 Up-or-down Free Running Counter 30
31 Up-or-down Free Running Counter (1) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity up_or_down_counter is generic( WIDTH: natural:=4; UP: natural:=0 ); port( clk, reset: in std_logic; q: out std_logic_vector(width-1 downto 0) ); end up_or_down_counter; 31
32 Up-or-down Free Running Counter (2) architecture arch of up_or_down_counter is signal r_reg: unsigned(width-1 downto 0); signal r_next: unsigned(width-1 downto 0); begin -- register process(clk,reset) begin if (reset='1') then r_reg <= (others=>'0'); elsif (clk'event and clk='1') then r_reg <= r_next; end if; end process; 32
33 Up-or-down Free Running Counter (3) -- next-state logic inc_gen: -- incrementor if UP=1 generate r_next <= r_reg + 1; end generate; dec_gen: --decrementor if UP/=1 generate r_next <= r_reg 1; end generate; -- output logic q <= std_logic_vector(r_reg); end arch; 33
34 Example 4 Up-and-down Free Running Counter 34
35 Up-and-down Free Running Counter 35
36 Up-and-down Free Running Counter (1) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity up_and_down_counter is generic(width: natural:=4); port( clk, reset: in std_logic; mode: in std_logic; q: out std_logic_vector(width-1 downto 0) ); end up_and_down_counter; 36
37 Up-and-down Free Running Counter (2) architecture arch of up_and_down_counter is signal r_reg: unsigned(width-1 downto 0); signal r_next: unsigned(width-1 downto 0); begin -- register process(clk,reset) begin if (reset='1') then r_reg <= (others=>'0'); elsif (clk'event and clk='1') then r_reg <= r_next; end if; end process; 37
38 Up-and-down Free Running Counter (3) -- next-state logic r_next <= r_reg + 1 when mode='1' else r_reg - 1; -- output logic q <= std_logic_vector(r_reg); end arch; 38
39 Example 5 Variable Rotator 39
40 Example 3: Variable rotator - Interface A 16 B 4 A <<< B 16 C 40
41 Block diagram 41
42 VHDL code for a 16-bit 2-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1_16 IS PORT ( w0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); w1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s : IN STD_LOGIC ; f : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END mux2to1_16 ; ARCHITECTURE dataflow OF mux2to1_16 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END dataflow ; 42
43 Fixed rotation a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) <<< 3 a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) y <= a(12 downto 0) & a(15 downto 13); a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) <<< 5 a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) a(12) a(11) y <= a(10 downto 0) & a(15 downto 11); 43
44 Fixed rotation by L positions a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) <<< L a(15-l) a(15-l-1) a(1) a(0) a(15) a(14) a(15-l+2) a(15-l+1) y <= a(15-l downto 0) & a(15 downto 15-L+1); 44
45 VHDL code for for a fixed 16-bit rotator LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fixed_rotator_left_16 IS GENERIC ( L : INTEGER := 1); PORT ( a : IN STD_LOGIC_VECTOR(15 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END fixed_rotator_left_16 ; ARCHITECTURE dataflow OF fixed_rotator_left_16 IS BEGIN y <= a(15-l downto 0) & a(15 downto 15-L+1); END dataflow ; 45
46 Structural VHDL code for for a variable 16-bit rotator (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY variable_rotator_16 is PORT( A : IN STD_LOGIC_VECTOR(15 downto 0); B : IN STD_LOGIC_VECTOR(3 downto 0); C : OUT STD_LOGIC_VECTOR(15 downto 0) ); END variable_rotator_16; 46
47 Structural VHDL code for for a variable 16-bit rotator (2) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ARCHITECTURE structural OF variable_rotator_16 IS COMPONENT mux2to1_16 PORT ( w0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); w1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s : IN STD_LOGIC ; f : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END COMPONENT ; COMPONENT fixed_rotator_left_16 GENERIC ( L : INTEGER := 1); PORT ( a : IN STD_LOGIC_VECTOR(15 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END COMPONENT ; 47
48 Structural VHDL code for for a variable 16-bit rotator (3) TYPE array1 IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(15 DOWNTO 0); TYPE array2 IS ARRAY (0 to 3) OF STD_LOGIC_VECTORS(15 DOWNTO 0); SIGNAL Al : array1; SIGNAL Ar : array2; BEGIN Al(0) <= A; G: FOR i IN 0 TO 3 GENERATE ROT_I: fixed_rotator_left_16 GENERIC MAP (L => 2** i) PORT MAP ( a => Al(i), y => Ar(i)); MUX_I: mux2to1_16 PORT MAP (w0 => Al(i), w1 => Ar(i), s => B(i), f => Al(i+1)); END GENERATE; C <= Al(4); END variable_rotator_16; 48
49 Block diagram 49
50 Example 6 XOR Tree 50
51 XOR Tree 51
52 XOR Tree (1) library ieee; use ieee.std_logic_1164.all; use work.util_pkg.all; entity reduced_xor is generic(width: natural:=8); port( a: in std_logic_vector(width-1 downto 0); y: out std_logic ); end reduced_xor; architecture gen_tree_arch of reduced_xor is constant STAGE: natural:= log2c(width); signal p: std_logic_2d(stage downto 0, WIDTH-1 downto 0); 52
53 XOR Tree (2) begin -- rename input signal in_gen: for i in 0 to (WIDTH-1) generate p(stage, i) <= a(i); end generate; -- replicated structure stage_gen: for s in (STAGE-1) downto 0 generate row_gen: for r in 0 to (2**s-1) generate p(s, r) <= p(s+1, 2*r) xor p(s+1, 2*r+1); end generate; end generate; -- rename output signal y <= p(0, 0); end gen_tree_arch; 53
54 util_pkg (1) library ieee; use ieee.std_logic_1164.all; package util_pkg is type std_logic_2d is array(integer range <>, integer range <>) of std_logic; function log2c (n: integer) return integer; end util_pkg ; 54
55 util_pkg (2) --package body package body util_pkg is function log2c(n: integer) return integer is variable m, p: integer; begin m := 0; p := 1; while p < n loop m := m + 1; p := p * 2; end loop; return m; end log2c; end util_pkg; 55
56 Array Data Type Array Type TYPE data_type_name IS ARRAY (range_1, range2,...) OF element_data_type; 56
57 XOR Tree with Arbitrary Input Size (1) begin -- rename input signal in_gen: for i in 0 to (WIDTH-1) generate p(stage,i) <= a(i); end generate; -- padding 0 s pad0_gen: if WIDTH < (2**STAGE) generate zero_gen: for i in WIDTH to (2**STAGE-1) generate p(stage,i) <= '0 ; end generate; end generate; 57
58 XOR Tree with Arbitrary Input Size (2) -- replicated structure stage_gen: for s in (STAGE-1) downto 0 generate row_gen: for r in 0 to (2**s-1) generate p(s,r) <= p(s+1,2*r) xor p(s+1,2*r+1); end generate; end generate; -- rename output signal y <= p(0,0); end gen_tree2_arch; 58
59 Unconstrained Array Types ECE 545 Introduction to VHDL 59
60 Predefined Unconstrained Array Types Predefined bit_vector array of bits string array of characters ECE 545 Introduction to VHDL 60
61 Predefined Unconstrained Array Types Defined in the std_logic_1164 package: type std_logic_vector is array (natural range <>) of std_logic; Defined in the numeric_std package: type unsigned is array (natural range <>) of bit; type signed is array (natural range <>) of bit; 61
62 Using Predefined Unconstrained Array Types subtype byte is bit_vector(7 downto 0);. signal channel_busy : bit_vector(1 to 4);. constant ready_message : string := ready ;. signal memory_bus: std_logic_vector (31 downto 0); 62
63 User-defined Unconstrained Array Types type std_logic_2d is array(integer range <>, integer range <>) of std_logic; signal s1: std_logic_2d(3 downto 0, 5 downto 0); signal s2: std_logic_2d(15 downto 0, 31 downto 0); signal s3: std_logic_2d(7 downto 0, 1 downto 0); 63
64 User-defined Unconstrained Array Type in a package use work.util_pkg.all; entity. generic ( ROW: natural; COL: natural) ); port ( p1: in std_logic_2d(row-1 downto 0, COL-1 downto 0);.. ) architecture signal s1: std_logic_2d(row-1 downto 0, COL-1 downto 0); 64
65 Array-of-Arrays Data Type constant ROW : natural := 4; constant COL : natural := 6; type sram_row_by_col is array (ROW -1 downto 0) of std_logic_vector(col 1 downto 0); signal t1: sram_row_by_col; signal v1: std_logic_vector(col-1 downto 0); signal b1: std_logic; t1 <= ( , , others => (others => 0 )); b1 <= t1(3)(0); v1 <= t1(2); 65
66 Attributes of Arrays and Array Types ECE 545 Introduction to VHDL 66
67 Array Attributes A left(n) left bound of index range of dimension N of A A right(n) right bound of index range of dimension N of A A low(n) lower bound of index range of dimension N of A A high(n) upper bound of index range of dimension N of A A range(n) index range of dimension N of A A reverse_range(n) reversed index range of dimension N of A A length(n) length of index range of dimension N of A A ascending(n) true if index range of dimension N of A is an ascending range, false otherwise 67
68 Array Attributes - Examples type A is array (1 to 4, 31 downto 0); A left(1) = 1 A right(2) = 0 A low(1) = 1 A high(2) = 31 A range(1) = 1 to 4 A length(2) = 32 A ascending(2) = false 68
69 Unconstrained PARITY Generator (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY parity IS PORT( parity_in ); END parity; : IN STD_LOGIC_VECTOR; parity_out : OUT STD_LOGIC 69
70 Unconstrained PARITY Generator (2) ARCHITECTURE parity_dataflow OF parity IS CONSTANT width: natural := parity_in length; SIGNAL xor_out: STD_LOGIC_VECTOR (width-1 DOWNTO 0); BEGIN xor_out(0) <= parity_in(0); G2: FOR i IN 1 TO 7 GENERATE xor_out(i) <= xor_out(i-1) XOR parity_in(i); END GENERATE G2; parity_out <= xor_out(width-1); END parity_dataflow; 70
71 Unconstrained PARITY Generator (3) Will the previous code work for the following types of signal parity_in? std_logic_vector(7 downto 0); std_logic_vector(0 to 7); std_logic_vector(15 downto 8); std_logic_vector(8 to 15); 71
72 Unconstrained PARITY Generator (4) ARCHITECTURE parity_dataflow OF parity IS CONSTANT width: natural := parity_in length; SIGNAL xor_out: STD_LOGIC_VECTOR (width-1 DOWNTO 0); SIGNAL pp: STD_LOGIC_VECTOR (width-1 DOWNTO 0); BEGIN pp <= parity_in; xor_out(0) <= pp(0); G2: FOR i IN 1 TO 7 GENERATE xor_out(i) <= xor_out(i-1) XOR pp(i); END GENERATE G2; parity_out <= xor_out(width-1); END parity_dataflow; 72
73 Aliases ECE 448 FPGA and ASIC Design with VHDL 73
74 Aliases Syntax: ALIAS name : type := expression; Example: signal IR : std_logic_vector(31 downto 0); alias IR_opcode : std_logic_vector(5 downto 0) is IR(31 downto 26); alias IR_reg1_addr : std_logic_vector(4 downto 0) is IR(25 downto 21); alias IR_reg2_addr : std_logic_vector(4 downto 0) is IR(20 downto 16); 74
75 Constants ECE 448 FPGA and ASIC Design with VHDL 75
76 Constants Syntax: CONSTANT name : type := value; Examples: CONSTANT init_value : STD_LOGIC_VECTOR(3 downto 0) := "0100"; CONSTANT ANDA_EXT : STD_LOGIC_VECTOR(7 downto 0) := X"B4"; CONSTANT counter_width : INTEGER := 16; CONSTANT buffer_address : INTEGER := 16#FFFE#; CONSTANT clk_period : TIME := 20 ns; CONSTANT strobe_period : TIME := ms; 76
77 Constants - features Constants can be declared in a PACKAGE, ENTITY, ARCHITECTURE When declared in a PACKAGE, the constant is truly global, for the package can be used in several entities. When declared in an ARCHITECTURE, the constant is local, i.e., it is visible only within this architecture. When declared in an ENTITY declaration, the constant can be used in all architectures associated with this entity. 77
78 Packages ECE 448 FPGA and ASIC Design with VHDL 78
79 Explicit Component Declaration versus Package Explicit component declaration is when you declare components in main code When have only a few component declarations, this is fine When have many component declarations, use packages for readability Packages also help with portability and sharing of libraries among many users in a company Remember, the actual instantiations always take place in main code Only the declarations can be in main code or package 79
80 Explicit Component Declaration Tips For simple projects put entity.vhd files all in same directory Declare components in main code If using Aldec, make sure compiler knows the correct hierarchy From lowest to highest Xilinx will figure out hierarchy automatically 80
81 METHOD #2: Package component declaration Components declared in package Actual instantiations and port maps always in main code 81
82 Packages Instead of declaring all components can declare all components in a PACKAGE, and INCLUDE the package once This makes the top-level entity code cleaner It also allows that complete package to be used by another designer A package can contain Components Functions, Procedures Types, Constants 82
83 Package example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE GatesPkg IS COMPONENT mux2to1 PORT (w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END COMPONENT ; COMPONENT priority PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z : OUT STD_LOGIC ) ; END COMPONENT ; 83
84 Package example (2) COMPONENT dec2to4 PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END COMPONENT ; COMPONENT regn GENERIC ( N : INTEGER := 8 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END COMPONENT ; 84
85 Package example (3) constant ADDAB : std_logic_vector(3 downto 0) := "0000"; constant ADDAM : std_logic_vector(3 downto 0) := "0001"; constant SUBAB : std_logic_vector(3 downto 0) := "0010"; constant SUBAM : std_logic_vector(3 downto 0) := "0011"; constant NOTA : std_logic_vector(3 downto 0) := "0100"; constant NOTB : std_logic_vector(3 downto 0) := "0101"; constant NOTM : std_logic_vector(3 downto 0) := "0110"; constant ANDAB : std_logic_vector(3 downto 0) := "0111"; END GatesPkg; 85
86 Package usage (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.gatespkg.all; ENTITY priority_resolver1 IS PORT (r : IN STD_LOGIC_VECTOR(5 DOWNTO 0) ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; clk : IN STD_LOGIC; en : IN STD_LOGIC; t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END priority_resolver1; ARCHITECTURE structural OF priority_resolver1 IS SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ; SIGNAL z : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL ena : STD_LOGIC ; 86
87 Package usage (2) BEGIN u1: mux2to1 PORT MAP ( w0 => r(0), w1 => r(1), s => s(0), f => p(0)); p(1) <= r(2); p(2) <= r(3); u2: mux2to1 PORT MAP ( w0 => r(4), w1 => r(5), s => s(1), f => p(3)); u3: priority PORT MAP ( w => p, y => q, z => ena); u4: dec2to4 PORT MAP ( w => q, En => ena, y => z); u5: regn GENERIC MAP ( N => 4) END structural; PORT MAP ( D => z, Enable => En, Clock => Clk, Q => t ); 87
88 Aldec Compilation Order Include package before top-level 88
89 Mixing Design Styles Inside of an Architecture ECE 448 FPGA and ASIC Design with VHDL 89
90 VHDL Design Styles VHDL Design Styles dataflow structural behavioral Concurrent statements synthesizable Components and Sequential statements interconnects Registers Shift registers Counters State machines 90
91 Mixed Style Modeling architecture ARCHITECTURE_NAME of ENTITY_NAME is Here you can declare signals, constants, types, etc. Component declarations begin Concurrent statements: Concurrent simple signal assignment Conditional signal assignment Selected signal assignment Generate statement Component instantiation statement Concurrent Statements Process statement inside process you can use only sequential statements end ARCHITECTURE_NAME; 91
92 PRNG Example (1) library IEEE; use IEEE.STD_LOGIC_1164.all; use work.prng_pkg.all; ENTITY PRNG IS PORT( Coeff : in std_logic_vector(4 downto 0); Load_Coeff : in std_logic; Seed : in std_logic_vector(4 downto 0); Init_Run : in std_logic; Clk : in std_logic; Current_State : out std_logic_vector(4 downto 0)); END PRNG; ARCHITECTURE mixed OF PRNG is signal Ands : std_logic_vector(4 downto 0); signal Sin : std_logic; signal Coeff_Q : std_logic_vector(4 downto 0); signal Shift5_Q : std_logic_vector(4 downto 0); 92
93 PRNG Example (2) -- Data Flow G: FOR I IN 0 TO 4 GENERATE Ands(I) <= Coeff_Q(I) AND Shift5_Q(I); END GENERATE; Sin <= Ands(0) XOR Ands(1) XOR Ands(2) XOR Ands(3) XOR Ands(4); Current_State <= Shift5_Q; -- Behavioral Coeff_Reg: PROCESS(Clk) BEGIN IF Clk'EVENT and Clk = '1' THEN IF Load_Coeff = '1' THEN Coeff_Q <= Coeff; END IF; END IF; END PROCESS; -- Structural Shift5_Reg : Shift5 PORT MAP ( D => Seed, Load => Init_Run, Sin => Sin, Clock => Clk, Q => Shift5_Q); END mixed; 93
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