search_chr: ASM chart search_chr search_chr search_chr MEM_ENABLE MEM_WE MEM_ADDRESS MEM_DATAIN MEM_DATAOUT MEM_READY ADDRESS CHAR LEN nfound
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1 ADDRESS CHAR LEN nfound ? START READY MEM_ENABLE MEM_WE MEM_ADDRESS MEM_DATAIN MEM_DATAOUT MEM_READY INIT COUNT <= 0 START : ASM chart A <= ADDRESS C <= CHAR L <= LEN CNT <= 0 FETCH MEM_READY COMPARE D <= MEM_DATAIN COUNT <= COUNT + 1 A <= A + 1!" #$% & ' ('')!!)'!!)!!% &'&&'! ''! *% & ' ' ) ) +,-$% START_READ nfound <- CNT MEM_ADDRESS <- A MEM_ENABLE <- 1 C = D 1 0 COUNT = LEN CNT <= CNT + 1 MEM_ADDRESS <- A MEM_ENABLE <- 1 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity is port ( CLK : in std_logic; rst_n : in std_logic; START : in std_logic; ADDRESS : in std_logic_vector(31 downto 0 CHAR : in std_logic_vector(7 downto 0 LEN : in std_logic_vector(5 downto 0 READY : out std_logic; nfound : out std_logic_vector(5 downto 0 MEM_ENABLE : out std_logic; MEM_WE : out std_logic; MEM_ADDRESS : out std_logic_vector(31 downto 0 MEM_DATAIN : in std_logic_vector(7 downto 0 MEM_DATAOUT : out std_logic_vector(7 downto 0 MEM_READY : in std_logic end ; architecture rtl of is write code write code end rtl;
2 Memory Memory library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use STD.textio.all; entity memory is port ( CLK : in std_logic; address : in std_logic_vector(31 downto 0 enable : in std_logic; we : in std_logic; ready : out std_logic; datain : in std_logic_vector(7 downto 0 dataout : out std_logic_vector(7 downto 0) end memory; architecture s of memory is type ram_type is array (0 to 1023) of bit_vector(7 downto 0 impure function loadmem return ram_type is file memory_file : text; variable fstatus : file_open_status; variable inputline : line; variable memory : ram_type; variable i : integer; file_open(fstatus, memory_file, "data.bin", READ_MODE if (fstatus = OPEN_OK) then i := 0; while (i < 1024 and not endfile(memory_file)) loop readline (memory_file, inputline read (inputline, memory(i) i := i + 1; end loop; return memory; end function; Memory end s; shared variable RAM : ram_type := loadmem; process(clk) if rising_edge(clk) and enable = '1' then if we = '1' then RAM(to_integer(unsigned(address))) := to_bitvector(datain dataout <= (others => '-' writing policy not specified dataout <= to_stdlogicvector(ram(to_integer(unsigned(address))) ready <= '1'; latency: 1 cycle Reset Generator rst_n Clock Generator CLK INPUTS OUTPUTS Inputs Generator (FSM) Memory Data File
3 : inputs generator INIT cnt <= 0 TEST1 START <- 1 ADDRESS <-... CHAR <-... LEN <-... cnt <= cnt+1 WAIT1 READY FINISHED1 cnt2 <= 0 FINISHED2 cnt <= cnt+1 cnt = 10 FINISHED3 end_simul <- true 0 cnt =... 1 terminate the clock generation process library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity testbench is end testbench; architecture behav of testbench is signal nsimul_cycles : integer := 0; signal started : boolean := false; signal end_simul : boolean := false; signal CLK : std_logic; signal rst_n : std_logic; type tb_statetype is (INIT, TEST1, WAIT1, FINISHED1, FINISHED2, FINISHED3 signal tb_state, tb_nextstate : tb_statetype; type array_of_integers is array (natural range <>) of integer; constant ADDRESSES : array_of_integers := ( 3, 5, 20 constant CHARS : array_of_integers := ( 3, 3, 5 constant LENS : array_of_integers := (10, 10, 15 signal START : std_logic; signal ADDRESS : std_logic_vector(31 downto 0 signal CHAR : std_logic_vector(7 downto 0 signal LEN : std_logic_vector(5 downto 0 signal READY : std_logic; signal nfound : std_logic_vector(5 downto 0 signal memory_enable : std_logic; signal memory_we : std_logic; signal memory_address : std_logic_vector(31 downto 0 signal data_from_mem : std_logic_vector(7 downto 0 signal data_to_mem : std_logic_vector(7 downto 0 signal memory_ready : std_logic; signal cnt, in_cnt, cnt2, in_cnt2 : integer := 0; start_process: process rst_n <= '1', '0' after 1 ns, '1' after 199 ns; started <= true; wait; clkgen: process clk <= '1', '0' after 5 ns; wait for 10 ns; if end_simul then wait; nsimul_cycles <= nsimul_cycles + 1 ;
4 DUT : entity work. port map ( CLK => CLK, rst_n => rst_n, START => START, ADDRESS => ADDRESS, CHAR => CHAR, LEN => LEN, READY => READY, nfound => nfound, MEM_ENABLE => memory_enable, MEM_WE => memory_we, MEM_ADDRESS => memory_address, MEM_DATAIN => data_from_mem, MEM_DATAOUT => data_to_mem, MEM_READY => memory_ready MEM : entity work.memory port map ( CLK => CLK, address => memory_address, enable => memory_enable, we => memory_we, ready => memory_ready, datain => data_to_mem, dataout => data_from_mem tb_state <= INIT when rst_n = '0' tb_nextstate when rising_edge(clk process (tb_state, READY, cnt, cnt2) case tb_state is when INIT => tb_nextstate <= TEST1; when TEST1 => tb_nextstate <= WAIT1; when WAIT1 => if READY = '1' then if cnt = ADDRESSES'length then tb_nextstate <= FINISHED1; tb_nextstate <= TEST1; tb_nextstate <= WAIT1; end case; when FINISHED1 => tb_nextstate <= FINISHED2; when FINISHED2 => if cnt2 = 10 then tb_nextstate <= FINISHED3; end_simul <= true; tb_nextstate <= FINISHED2; when FINISHED3 => tb_nextstate <= FINISHED3;
5 START <= '1' when tb_state = TEST1 '0'; ADDRESS <= std_logic_vector(to_unsigned(addresses(cnt), ADDRESS'length)) when tb_state = TEST1 (others => '-' CHAR <= std_logic_vector(to_unsigned(chars(cnt), CHAR'length)) when tb_state = TEST1 (others => '-' LEN <= std_logic_vector(to_unsigned(lens(cnt), LEN'length)) when tb_state = TEST1 (others => '-' in_cnt <= 0 when tb_state = INIT cnt + 1 when tb_state = TEST1 0; cnt <= in_cnt when rising_edge(clk) and (tb_state = INIT or tb_state = TEST1 in_cnt2 <= 0 when tb_state = FINISHED1 cnt2 + 1 when tb_state = FINISHED2 0; cnt2 <= in_cnt2 when rising_edge(clk) and (tb_state = FINISHED1 or tb_state = FINISHED2 end behav; Data for simulation (example) Simulation results (continue) data.bin (second portion) first search: found 2 characters
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