Contents Part I Basic Concepts The Nature of Hardware and Software Data Flow Modeling and Transformation

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1 Contents Part I Basic Concepts 1 The Nature of Hardware and Software Introducing Hardware/Software Codesign Hardware Software Hardware and Software Defining Hardware/Software Codesign The Quest for Energy Efficiency Performance Energy Efficiency The Driving Factors in Hardware/Software Codesign The Hardware-Software Codesign Space The Platform Design Space Application Mapping The Dualism of Hardware Design and Software Design Modeling Abstraction Level Concurrency and Parallelism Summary Further Reading Problems Data Flow Modeling and Transformation Introducing Data Flow Graphs Tokens, Actors, and Queues Firing Rates, Firing Rules, and Schedules Synchronous Data Flow (SDF) Graphs SDF Graphs are Determinate Analyzing Synchronous Data Flow Graphs Deriving Periodic Admissible Sequential Schedules Example: Deriving a PASS for the PAM-4 System xv

2 xvi Contents 2.3 Control Flow Modeling and the Limitations of Data Flow Models Emulating Control Flow with SDF Semantics Extending SDF Semantics Adding Time and Resources Real-Time Constraints and Input/Output Sample Rate Data Flow Resource Model Limits on Throughput Transformations Multirate Expansion Retiming Pipelining Unfolding Data Flow Modeling Summary Further Reading Problems Data Flow Implementation in Software and Hardware Software Implementation of Data Flow Converting Queues and Actors into Software Software Implementation with a Dynamic Scheduler Example: Four-Point Fast Fourier Transform as an SDF System Sequential Targets with Static Schedule Hardware Implementation of Data Flow Single-Rate SDF Graphs into Hardware Pipelining Hardware/Software Implementation of Data Flow Summary Further Reading Problems Analysis of Control Flow and Data Flow Data and Control Edges of a C Program Implementing Data and Control Edges Construction of the Control Flow Graph Construction of the Data Flow Graph Application: Translating C to Hardware Designing the Datapath Designing the Controller Single-Assignment Programs Summary Further Reading Problems

3 Contents xvii Part II The Design Space of Custom Architectures 5 Finite State Machine with Datapath Cycle-Based Bit-Parallel Hardware Wires and Registers Precision and Sign Hardware Mapping of Expressions Hardware Modules Finite State Machines Finite State Machines with Datapath Modeling The FSMD Model As Two Stacked FSM An FSMD Is Not Unique Implementation FSMD Design Example: A Median Processor Design Specification: Calculating the Median Mapping the Median in Hardware Sequentializing the Data Input Fully Sequentialized Computation Proper FSMD Language Mapping for FSMD by Example GCD in GEZEL GCD in Verilog GCD in VHDL GCD in SystemC Summary Further Reading Problems Microprogrammed Architectures Limitations of Finite State Machines State Explosion Exception Handling Runtime Flexibility Microprogrammed Control Micro-instruction Encoding Jump Field Command Field The Micro-programmed Datapath Datapath Architecture Writing Micro-programs Implementing a Micro-programmed Machine Micro-instruction Word Definition Micro-program Interpreters

4 xviii Contents 6.7 Micro-program Pipelining Micro-instruction Register Datapath Condition-Code Register Pipelined Next-Address Logic Microprogramming with Microcontrollers System Architecture Example: Bresenham Line Drawing Summary Further Reading Problems General-Purpose Embedded Cores Processors The Toolchain of a Typical Micro-processor From C to Assembly Instructions The RISC Pipeline Control Hazards Data Hazards Structural Hazards Program Organization Data Types Variables in the Memory Hierarchy Function Calls Program Layout Compiler Tools Examining Size Examining Sections Examining Assembly Code Low-Level Program Analysis Processor Simulation Instruction-Set Simulation Analysis Based on Execution of Object Code Simulation at Low Abstraction Level Summary Further Reading Problems Systemon Chip The System-on-Chip Concept The Cast of Players SoC Interfaces for Custom Hardware Four Design Principles in SoC Architecture Heterogeneous and Distributed Data Processing Heterogeneous and Distributed Communications Heterogeneous and Distributed Storage Hierarchical Control

5 Contents xix 8.3 Example: Portable Multimedia System SoC Modeling in GEZEL An SoC with a StrongARM Core Ping-Pong Buffer with an UART on the AVR ATMega Summary Further Reading Problems Part III Hardware/Software Interfaces 9 Principles of Hardware/Software Communication Connecting Hardware and Software Synchronization Schemes Synchronization Concepts Semaphore One-Way and Two-Way Handshake Blocking and Non-blocking Data-Transfer Communication-Constrained Versus Computation-Constrained Tight and Loose Coupling Summary Further Reading Problems On-Chip Busses On-Chip Bus Systems A Few Existing On-Chip Bus Standards Elements in a Shared Bus Elements in a Point-to-Point Bus Physical Implementation of On-Chip Busses Bus Naming Convention Bus Timing Diagram Definition of the Generic Bus Bus Transfers Simple Read and Write Transfers Transfer Sizing and Endianess Improved Bus Transfers Multi-master Bus Systems Bus Priority Bus Locking Bus Topologies Bus Switches Network On Chip Summary

6 xx Contents 10.6 Further Reading Problems Microprocessor Interfaces Memory-Mapped Interfaces The Memory-Mapped Register Mailboxes First-In First-Out Queues Slave and Master Handshakes Shared Memory GEZEL Modeling of Memory-Mapped Interfaces Coprocessor Interfaces The Fast Simplex Link The LEON-3 Floating Point Coprocessor Interface Custom-Instruction Interfaces ASIP Design Flow Example: Endianness Byte-Ordering Processor Example: The Nios-II Custom-Instruction Interface Finding Good ASIP Instructions Summary Further Reading Problems Hardware Interfaces The Coprocessor Hardware Interface Functions of the Coprocessor Hardware Interface Layout of the Coprocessor Hardware Interface Data Design Flexible Addressing Mechanisms Multiplexing and Masking Control Design Hierarchical Control Control of Internal Pipelining Programmer s Model = Control Design + Data Design Address Map Instruction Set Summary Further Reading Problems Part IV Applications 13 Trivium Crypto-Coprocessor The Trivium Stream Cipher Algorithm Stream Ciphers Trivium

7 Contents xxi Hardware Mapping of Trivium A Hardware Testbench for Trivium Trivium for 8-bit Platforms Overall Design of the 8051 Coprocessor Hardware Platform of the 8051 Coprocessor Software Driver for Trivium for 32-bit Platforms Hardware Platform Using Memory-Mapped Interfaces Software Driver Using Memory-Mapped Interfaces Hardware Platform Using a Custom-Instruction Interface Software Driver for a Custom-Instruction Interface Summary Further Reading Problems AES Co-processor AES Encryption and Decryption Memory-Mapped AES Encryption Coprocessor Hardware Interface Operation Programmer s Model Software Driver Design Hardware Interface Design System Performance Evaluation AES Encryption/Decryption with Custom Instructions AES T-box Reference Implementation AES T-box Custom Instruction Design AES T-box Custom Instruction in GEZEL AES T-box Software Integration and Performance Summary Further Reading Problems CORDIC Co-processor The Coordinate Rotation Digital Computer Algorithm The Algorithm Reference Implementation in C A Hardware Coprocessor for CORDIC A CORDIC Kernel in Hardware A Hardware Interface for Fast-Simplex-Link Coprocessors An FPGA Prototype of the CORDIC Coprocessor Handling Large Amounts of Rotations Summary

8 xxii Contents 15.6 Further Reading Problems A Hands-on Experiments in GEZEL A.1 Overview of the GEZEL Tools A.2 Installing the GEZEL Tools A.2.1 Installation on a Ubuntu System A.2.2 Installation of Cross-Compiler Tools A.2.3 Compiling GEZEL from Source Code on a 32-bit System A.2.4 Compiling GEZEL from Source Code on a 64-bit System A.3 Running the Examples A.3.1 Examples from FSMD Chapter A.3.2 Examples from Microprogrammed Architectures Chapter A.3.3 Examples from System on Chip Chapter A.3.4 Examples from Microprocessor Interfaces Chapter A.3.5 Examples from Trivium Chapter A.3.6 Examples from AES Chapter A.3.7 Examples from CORDIC Chapter References Index

A Practical Introduction to Hardware/Software Codesign

A Practical Introduction to Hardware/Software Codesign Patrick R. Schaumont A Practical Introduction to Hardware/Software Codesign 123 Dr. Patrick R. Schaumont Virginia Tech Bradley Dept. Electrical &