Digital Design. Chapter 4: Datapath Components

Transcription

1 Digitl Design Chpter 4: Dtpth Components Slides to ccompny the textbook Digitl Design, with RTL Design, VHDL, nd Verilog, 2nd Edition, by, John Wiley nd Sons Publishers, 2. Copyright 2 Instructors of courses requiring Vhid's Digitl Design textbook (published by John Wiley nd Sons) hve permission to modify nd use these slides for customry course-relted ctivities, subject to keeping this copyright notice in plce nd unmodified. These slides my be posted s unnimted pdf versions on publicly-ccessible course websites.. PowerPoint source (or pdf with nimtions) Digitl my Design not be posted 2e to publicly-ccessible websites, but my be posted for students on internl protected sites or distributed directly to students by other electronic mens. Instructors my Copyright mke printouts 2 of the slides vilble to students for resonble photocopying chrge, without incurring roylties. Any other use requires explicit permission. Instructors my obtin PowerPoint source or obtin specil use permissions from Wiley see for informtion.

2 Introduction 4. Chpts 2 & 3: Introduced incresingly complex digitl building blocks Gtes, multiplexors, decoders, bsic registers, nd controllers Controllers good for systems with control inputs/outputs Control input: Single bit (or few), representing environment event or stte Ex: bit representing button pressed Dt input: Multiple bits representing single entity Ex: 7 bits representing temperture in binry Need ppropite building blocks for dt Dtpth components (register-trnsfer-level, or RTL) components: store/trnsform dt Combine dtpth components to form dtpth Chpt 4 introduces some dtpth components nd simple dtpths Next chpter will combine controllers nd dtpths into processors Digitl Design 2e Copyright 2 Note: Slides with nimtion re denoted with smll red "" ner the nimted items Approprite building blocks: Tires, set, pedls Not: Rubber, glue, metl 2

3 Registers 4.2 N-bit register: Stores N bits, N is the width Common widths:, 6, 32 Storing dt into register: Loding Opposite of storing: Reding (does not lter contents) Bsic register of Ch 3: Loded every cycle Useful for implementing FSM stores encoded stte b clk Combintionl logic s s Stte register n n x lod clk I3 D Q I2 D Q I D Q I 4-bit register D Q I3 I2 I I reg(4) Q3 Q2 Q Q Q3 Q2 Q Q Bsic register lods on every clock cycle How extend to only lod on certin cycles? Digitl Design 2e Copyright 2 3

4 Register with Prllel Lod Add 2x mux to front of ech flip-flop Register s lod input selects mux input to pss lod=: existing flip-flop vlue; lod=: new input vlue I3 I2 I I lod 2x D Q Q3 D Q Q2 D Q Q D Q Q I3 I2 I I lod Q3 Q2 Q Q block symbol lod= I3 D I2 D I D I D lod= I3 D I2 D I D I D Q Q Q Q Q Q Q Q Digitl Design 2e Copyright 2 Q3 Q2 Q Q Q3 Q2 Q Q 4

5 Register Exmple using the Lod Input: Weight Smpler Scle hs two displys Present weight Sved weight Useful to compre present item with previous item Use 4-bit prllel lod register to store weight Pressing button lods present weight into register Register contents lwys displyed s Sved weight, even when new present weight ppers Scle 3 pounds Sved weight Weight Smpler Sve b I3 I2 I I 32 pounds lod Present weight clk Q3 Q2 Q Q Digitl Design 2e Copyright 2 5

6 Buses N-bit bus: N wires to crry N-bit dt item Scle Weight Smpler Circuit drwings cn become cluttered Sve b lod I3 I2 I I Convention for drwing buses Present weight clk Q3 Q2 Q Q Single bold line nd/or smll ngled line cross Sved weight ld Digitl Design 2e Copyright 2 6

7 Register Exmple: Above-Mirror Disply C d lod reg T Loded on clock edge Ch2 ex: Four simultneous vlues from cr s computer To reduce wires: Computer writes only vlue t time, lods into one of four registers Ws: +++ = 32 wires Now: +2+ = wires Digitl Design 2e Copyright 2 lod 2x4 d i i d2 d3 e lod reg lod reg2 lod reg3 A I M i i i2 -bit 4 d i3 s s x y 7 D

8 Register Exmple: Computerized Checkerbord Ech register holds vlues for one column of LEDs lights LED Microprocessor lods one register t time Occurs fst enough tht user sees entire bord chnge t once R7 d7 R6 d6 R5 d5 R4 d4 R3 d3 R2 d2 R d R d e i2 i i 3x decoder D microprocessor () LED Q lit LED from microprocessor I R lod from decoder (b) Digitl Design 2e Copyright 2

9 Register Exmple: Computerized Checkerbord LED lit LED R7 R6 R5 R4 R3 R2 R R D i2,i,i e clk (R) (R) (R2) (R3) (R4) (R5) (R6) (R7) Digitl Design 2e Copyright 2 9

10 Shift Register Shift right Move ech bit one position right Rightmost bit is dropped Assume shifted into leftmost bit Register contents before shift right Register contents fter shift right Q: Do four right shifts on, showing vlue fter ech shift A: (originl) Implementtion: Connect flip-flop output to next flip-flop s input shr_in Digitl Design 2e Copyright 2

11 Shift Register To llow register to either shift or retin, use 2x muxes shr: mens retin, shift shr_in: vlue to shift in My be, or shr_in shr 2x D Q Q3 D Q Q2 D Q Q D Q Q () Left-shift register lso esy to design shr= 2x D Q Q3 shr_in shr D Q Q2 (b) D Q Q Q3 Q2 Q Q D Q Q Digitl Design 2e Copyright 2 (c)

12 Rotte Register Rotte right: Like shift right, but leftmost bit comes from rightmost bit Register contents before shift right Register contents fter shift right Digitl Design 2e Copyright 2 2

13 Shift Register Exmple: Above-Mirror Disply Erlier exmple: +2+ = wires from cr s computer to bove-mirror disply s four registers Better thn 32 wires, but still lot wnt fewer for smller wire bundles Use shift registers Wires: +2+=4 Computer sends one vlue t time, one bit per clock cycle Digitl Design 2e Copyright 2 From the cr's centrl computer e d3 lod C d 2 4 d i i d2 d3 e lod lod lod lod reg reg reg2 reg3 T A I M i -bit 4 i i2 d i3 s s Note: this line is wire, rther thn like before c x y shr_in d shr reg T s s 2x4 i shr_in 4 d shr reg A i i i shr_in d d2 shr reg2 I shift shr_in shr reg3 M x i2 i3 y 3 To the bove mirror disply D D

14 Multifunction Registers Mny registers hve multiple functions Lod, shift, cler (lod ll s) And retin present vlue, of course Esily designed using muxes Just connect ech mux input to chieve desired function s s Functions: Opertion Mintin present vlue Prllel lod Shift right (unused - let's lod s) shr_in I3 I2 I I s s 3 2 4x D Q 3 2 D Q 3 2 D Q 3 2 D Q shr_in s s I3 Q3 I2 I I Q2 Q Q Q3 Q2 Q Q (b) Digitl Design 2e Copyright 2 () 4

15 Multifunction Registers s s Opertion Mintin present vlue Prllel lod Shift right Shift left I3 I2 I I shr_in shl_in 3 2 D 3 2 D 3 2 D 3 2 D shl_in shr_in s s I3 I2 I I Q Q Q Q Q3 Q2 Q Q Q3 Q2 () Q Q (b) Digitl Design 2e Copyright 2 5

16 Multifunction Registers with Seprte Control Inputs ld shr shl Truth tble for combintionl circuit Inputs ld shr shl Opertion Mintin present vlue Shift left Shift right Shift right shr hs priority over shl Prllel lod Prllel lod ld hs priority Prllel lod ld hs priority shr_in Prllel lod ld hs priority ld Outputs s s Note Opertion Mintin vlue Shift left Shift right Shift right Prllel lod Prllel lod Prllel lod Prllel lod shr shl combintionl? circuit shr_in s s I3 Q3 I3 Q3 I2 I I I2 I I shl_in Q2 Q Q Q2 Q Q shl_in s = ld *shr *shl + ld *shr*shl + ld *shr*shl s = ld *shr *shl + ld s s Opertion Mintin present vlue Prllel lod Shift right Shift left Digitl Design 2e Copyright 2 6

17 Register Opertion Tble Register opertions typiclly shown using compct version of tble X mens sme opertion whether vlue is or One X expnds to two rows Two Xs expnd to four rows Put highest priority control input on left to mke reduced tble simple Inputs ld shr shl Outputs s s Note Opertion ld shr shl Opertion Mintin vlue Shift left Shift right Shift right Prllel lod Prllel lod Prllel lod Prllel lod X X X Mintin vlue Shift left Shift right Prllel lod Digitl Design 2e Copyright 2 7

18 Register Design Process Cn design register with desired opertions using simple four-step process Digitl Design 2e Copyright 2

19 Digitl Design 2e Copyright 2 Register Design Exmple Desired register opertions Lod, shift left, synchronous cler, synchronous set Wnt unique control input for ech opertion Step : Determine mux size 5 opertions: bove, plus mintin present vlue (don t forget this one!) Use x mux Step 2: Crete mux opertion tble Step 3: Connect mux inputs Step 4: Mp control lines s2 = clr *set s = clr *set *ld *shl + clr s = clr *set *ld + clr clr Inputs set ld X X X s2 s s shl X X X s2 s Outputs s2 s s s D Q Opertion Mintin present vlue Prllel lod Shift left Synchronous cler Synchronous set Mintin present vlue Mintin present vlue Mintin present vlue Qn In Opertion Mintin present vlue Shift left Prllel lod Set to ll s Cler to ll s 9 from Qn-

20 Register Design Exmple I3 I2 I I shl ld set clr combintionl circuit s2 s s I3 Q3 I2 I I shl_in Q2 Q Q shl_in Q3 Q2 Q Q Step 4: Mp control lines s2 = clr *set s = clr *set *ld *shl + clr s = clr *set *ld + clr Digitl Design 2e Copyright 2 clr Inputs set ld X X X shl X X X Outputs s2 s s Opertion Mintin present vlue Shift left Prllel lod Set to ll s Cler to ll s 2

21 Digitl Design 2e Copyright 2 2 Adders Adds two N-bit binry numbers 2-bit dder: dds two 2-bit numbers, outputs 3-bit result e.g., + = ( + 3 = 4) Cn design using combintionl design process of Ch 2, but doesn t work well for typicl N Why not? 4.3 s s c b b Inputs Outputs

22 Why Adders Aren t Built Using Stndrd Digitl Design 2e Copyright 2 Combintionl Design Process Truth tble too big 2-bit dder s truth tble shown Hs 2 (2+2) = 6 rows -bit dder: 2 (+) = 65,536 rows 6-bit dder: 2 (6+6) = ~4 billion rows 32-bit dder:... Big truth tble with numerous s/s yields big logic Plot shows number of trnsistors for N-bit dders, using stte-of-the-rt utomted combintionl design tool Q: Predict number of trnsistors for 6-bit dder A: trnsistors for N=5, doubles for ech increse of N. So trnsistors = *2 (N-5). Thus, for N=6, trnsistors = *2 (6-5) = *24 = 2,4,. Wy too mny! Inputs N Size comes from implementing with two levels of gtes. Following pproch uses more levels to chieve smller size. Trnsistors b b c Outputs s s

23 Alterntive Method to Design n Adder: Imitte Adding by Hnd Alterntive dder design: mimic how people do ddition by hnd One column t time Compute sum, dd crry to next column A: B: Digitl Design 2e Copyright 2 23

24 Alterntive Method to Design n Adder: Imitte Crete component for ech column Adds tht column s bits, genertes sum nd crry bits Adding by Hnd A: B: + A: + B: b ci b ci b ci b co s co s co s co s SUM Digitl Design 2e Copyright 2 Full-dders Hlf-dder 24

25 Hlf-Adder Hlf-dder: Adds 2 bits, genertes sum nd crry Design using combintionl design process from Ch 2 Step : Cpture the function Inputs b Outputs co s A: + B: b ci co s b ci co s b ci co s b co s SUM Step 2A: Crete equtions co = b s = b + b (sme s s = xor b) b b Hlf-dder (HA) Step 2B: Implement s circuit co () s co (b) s Digitl Design 2e Copyright 2 25

26 Digitl Design 2e Copyright 2 Full-Adder Full-dder: Adds 3 bits, genertes sum nd crry Design using combintionl design process from Ch 2 A: + B: Step : Cpture the function Step 2A: Crete equtions Inputs b ci Outputs co s b ci co s co = bc + b c + bc + bc co = bc +bc +b c +bc +bc +bc co = ( +)bc + (b +b)c + (c +c)b co = bc + c + b s = b c + bc + b c + bc s = (b c + bc ) + (b c + bc) s = (b xor c) + (b xor c) s = xor b xor c b ci co s b ci co s b co s SUM Step 2B: Implement s circuit b Full dder (FA) co ci s 26

27 Crry-Ripple Adder Using hlf-dder nd full-dders, we cn build dder tht dds like we would by hnd Clled crry-ripple dder 4-bit dder shown: Adds two 4-bit numbers, genertes 5-bit output 5-bit output cn be considered 4-bit sum plus -bit crry out Cn esily build ny size dder 3 b3 2 b2 b b b FA co ci s b FA co ci s b FA co ci s co b HA s 32 b3b2bb 4-bit dder co s3 s2 s s co s3 s2 s () s (b) Digitl Design 2e Copyright 2 27

28 Crry-Ripple Adder Using full-dder insted of hlf-dder for first bit, we cn include crry in bit in the ddition Useful lter when we connect smller dders to form bigger dders 3 b3 2 b2 b b ci b ci b ci b ci b ci 32 b3b2bb FA FA FA FA 4-bit dder ci co s co s co s co s co s3 s2 s s co s3 s2 s () s (b) Digitl Design 2e Copyright 2 2

29 Crry-Ripple Adder s Behvior b ci FA co s b ci b ci b ci FA FA FA co s co s co s Assume ll inputs initilly Digitl Design 2e Copyright 2 + b ci FA b ci FA b ci FA b ci FA co s co s co s co s co2 co co (nswer should be ) Output fter 2 ns (FA dely) Wrong nswer is there problem? No just need more time for crry to ripple through the chin of full dders. 29

30 Crry-Ripple Adder s Behvior b ci b ci b ci b ci FA FA FA FA co s co s co s co s co (b) + (nswer should be ) Outputs fter 4ns (2 FA delys) b ci b ci b ci b ci FA FA FA FA co s co s co s co s co2 (c) Outputs fter 6ns (3 FA delys) Digitl Design 2e Copyright 2 b ci FA co s b ci b ci b ci FA FA FA co s co s co s (d) Correct nswer ppers fter 4 FA delys Output fter ns (4 FA delys) 3

31 Cscding Adders 7654 b7b6b5b4 32 b3b2bb 32 b3b2bb 4-bit dder ci 32 b3b2bb 4-bit dder ci 7.. b7.. b -bit dder ci + co s3 s2 s s co s3 s2 s s co s7.. s co s7 s6 s5 s4 () s3 s2 s s (b) C (c) Block symbol Simplified block symbol Digitl Design 2e Copyright 2 3

32 Adder Exmple: DIP-Switch-Bsed Adding Clcultor Gol: Crete clcultor tht dds two -bit binry numbers, specified using DIP switches DIP switch: Dul-inline pckge switch, move ech switch up or down Solution: Use -bit dder DIP switches co 7.. b7..b -bit crry-ripple dder s7..s ci CALC LEDs Digitl Design 2e Copyright 2 32

33 Adder Exmple: DIP-Switch-Bsed Adding Clcultor To prevent spurious vlues from ppering t output, cn plce register t output Actully, the light flickers from spurious vlues would be too fst for humns to detect but the principle of registering outputs to void spurious vlues being red by externl devices (which normlly ren t humns) pplies here. DIP switches 7.. b7..b -bit dder ci co s7..s clk e ld -bit register CALC Digitl Design 2e Copyright 2 LEDs 33

34 Adder Exmple: Compensting Weight Scle Weight scle with compenstion mount of -7 To compenste for inccurte sensor due to physicl wer Use -bit dder weight sensor Dil, cn be set by user 7.. b7..b -bit dder ci co s7..s clk ld disply register Weight Adjuster Digitl Design 2e Copyright 2 to disply 34

35 Incrementer Adds to input A 3 Inputs 2 c s3 Outputs s2 s s crries: unused () co b HA co s s3 b HA co s s2 b HA co s s b HA co s s Incrementer (+) co s3 s2 s s (b) Could design using combintionl design process, but smller design uses crry-ripple, only need hlf-dders Digitl Design 2e Copyright 2 35

36 Comprtors 4.4 N-bit equlity comprtor: Outputs if two N-bit numbers re equl 4-bit equlity comprtor with inputs A nd B 3 must equl b3, 2 = b2, = b, = b Two bits re equl if both, or both eq = (3b3 + 3 b3 ) * (2b2 + 2 b2 ) * (b + b ) * (b + b ) Note tht function inside prentheses is XNOR eq = (3 xnor b3) * (2 xnor b2) * ( xnor b) * ( xnor b) 3 b3 2 b2 b b =? 32 b3b2bb 4-bit equlity comprtor eq = eq Digitl Design 2e Copyright 2 36

37 Mgnitude Comprtor N-bit mgnitude comprtor: Two N-bit inputs A nd B, outputs whether A>B, A=B, or A<B, for How design? Consider compring by hnd. First compre 3 nd b3. If equl, compre 2 nd b2. And so on. Stop if comprison not equl (the two bits re nd, or nd ) whichever of A or B hs the is thus greter. If never see unequl bit pir, then A=B. A= B= Equl Equl Not equl So A > B Digitl Design 2e Copyright 2 37

38 Mgnitude Comprtor By-hnd exmple leds to ide for design Strt t left, compre ech bit pir, pss results to the right Ech bit pir clled stge Ech stge hs 3 inputs tking results of higher stge, outputs new results to lower stge 3 b3 2 b2 b b b b b b Igt Ieq Ilt in_gt in_eq in_lt out_gt out_eq out_lt in_gt in_eq in_lt out_gt out_eq out_lt in_gt in_eq in_lt out_gt out_eq out_lt in_gt in_eq in_lt out_gt out_eq out_lt AgtB AeqB AltB Stge 3 Stge 2 Stge Stge How design ech stge? Digitl Design 2e Copyright 2 Igt Ieq Ilt 32 b3b2bb AgtB AeqB AltB 4-bit mgnitude comprtor > = < 3

39 Mgnitude Comprtor 3 b3 2 b2 b b b b b b Igt Ieq Ilt in_gt in_eq in_lt out_gt out_eq out_lt in_gt in_eq in_lt out_gt out_eq out_lt in_gt in_eq in_lt out_gt out_eq out_lt in_gt in_eq in_lt out_gt out_eq out_lt AgtB AeqB AltB Stge 3 Stge 2 Stge Stge Ech stge: out_gt = in_gt + (in_eq * * b ) A>B if lredy determined in higher stge, or if higher stges equl but in this stge = nd b= out_lt = in_lt + (in_eq * * b) A<B if lredy determined in higher stge, or if higher stges equl but in this stge = nd b= out_eq = in_eq * ( XNOR b) A=B (so fr) if lredy determined in higher stge nd in this stge =b too Simple circuit inside ech stge, just few gtes (not shown) Digitl Design 2e Copyright 2 39

40 Mgnitude Comprtor How does it work? =? = 3 b3 2 b2 b b Ieq= cuses this stge to compre Igt Ieq Ilt in_gt in_eq in_lt b out_gt out_eq out_lt in_gt in_eq in_lt b out_gt out_eq out_lt in_gt in_eq in_lt b out_gt out_eq out_lt in_gt in_eq in_lt b out_gt out_eq out_lt AgtB AeqB AltB Stge3 Stge2 () Stge Stge = 3 b3 2 b2 b b Igt Ieq Ilt in_gt in_eq in_lt b out_gt in_gt out_eq in_eq out_lt in_lt b out_gt out_eq out_lt in_gt in_eq in_lt b out_gt out_eq out_lt in_gt in_eq in_lt b out_gt out_eq out_lt AgtB AeqB AltB Digitl Design 2e Copyright 2 Stge3 Stge2 (b) Stge Stge 4

41 Mgnitude Comprtor =? > 3 b3 2 b2 b b Igt in_gt out_gt in_gt out_gt Ieq in_eq out_eq in_eq out_eq Ilt in_lt out_lt in_lt out_lt b b in_gt out_gt in_eq out_eq in_lt out_lt b b in_gt out_gt in_eq out_eq in_lt out_lt Stge3 Stge2 Stge Stge (c) 3 b3 2 b2 b b b b b b Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AgtB AeqB AltB AgtB AeqB AltB Finl nswer ppers on the right Tkes time for nswer to ripple from left to right Thus clled crry-ripple style fter the crry-ripple dder Even though there s no crry involved Digitl Design 2e Copyright 2 Stge3 Stge2 (d) Stge Stge 4

42 Mgnitude Comprtor Exmple: Minimum of Two Numbers Design combintionl component tht computes the minimum of two -bit numbers Solution: Use -bit mgnitude comprtor nd -bit 2x mux If A<B, pss A through mux. Else, pss B. MIN A B Igt Ieq Ilt A B -bit mgnitude comprtor () AgtB AeqB AltB s I I -bit 2x mux C A B Min C (b) Digitl Design 2e Copyright 2 42

43 Multiplier Arry Style 4.5 Cn build multiplier tht mimics multipliction by hnd Notice tht multiplying multiplicnd by is sme s ANDing with Digitl Design 2e Copyright 2 43

44 Multiplier Arry Style Generlized representtion of multipliction by hnd Digitl Design 2e Copyright 2 44

45 Multiplier design rry of AND gtes Multiplier Arry Style 3 2 b pp b pp2 b2 + (5-bit) b3 pp4 pp3 + (6-bit) A * P B + (7-bit) Block symbol Digitl Design 2e Copyright 2 p7..p 45

46 Subtrctors nd Signed Numbers Cn build subtrctor s we built crry-ripple dder Mimic subtrction by hnd Compute the borrows from columns on left Use full-subtrctor component: wi is borrow by column on right, wo borrow from column on left - st column - 2nd column 3rd column - - 4th column b3 2 b2 b b wi b wi b wi b wi b wi 3 2 b3 b2 b b FS FS FS FS 4-bit subtrctor wi wo s wo s wo s wo s wo s3s2ss wo s3 s2 (b) s s (c) Digitl Design 2e Copyright 2 46

47 Subtrctor Exmple: DIP-Switch Bsed Adding/Subtrcting Clcultor Extend erlier clcultor exmple Switch f indictes whether wnt to dd (f=) or subtrct (f=) Use subtrctor nd 2x mux clk f e A B -bit dder co S ld ci DIP switches A B wi -bit subtrctor wo S 2x -bit register CALC LEDs Digitl Design 2e Copyright 2 47

48 Subtrctor Exmple: Color Spce Converter RGB to CMYK Color Often represented s weights of three colors: red, green, nd blue (RGB) Perhps bits ech (-255), so specific color is 24 bits White: R= (255), G=, B= Blck: R=, G=, B= Other colors: vlues in between, e.g., R=, G=, B= would be reddish purple Good for computer monitors, which mix red, green, nd blue lights to form colors Printers use opposite color scheme Becuse inks bsorb light Use complementry colors of RGB: Cyn (bsorbs red), reflects green nd blue, Mgent (bsorbs green), nd Yellow (bsorbs blue) Digitl Design 2e Copyright 2 4

49 Subtrctor Exmple: Color Spce Converter RGB to CMYK Printers must quickly convert RGB to CMY C=255-R, M=255-G, Y=255-B Use subtrctors s shown R G B C M Y Digitl Design 2e Copyright 2 49

50 Subtrctor Exmple: Color Spce Converter RGB to CMYK Try to sve colored inks Expensive Imperfect mixing C, M, Y doesn t yield good-looking blck Solution: Fctor out the blck or gry from the color, print tht prt using blck ink e.g., CMY of (25,2,2)= (2,2,2) + (5,,). (2,2,2) is drk gry use blck ink Digitl Design 2e Copyright 2 5

51 Cll blck prt K Subtrctor Exmple: Color Spce Converter RGB to CMYK (2,2,2): K=2 (Letter B lredy used for blue) Compute minimum of C, M, Y vlues R G B R G B RGB to CMY C M Y Use MIN component designed erlier, using C M Y comprtor nd mux, to MIN compute K Output resulting K vlue, nd subtrct K vlue from MIN C, M, nd Y vlues K Ex: Input of (25,2,2) yields output of (5,,,2) Digitl Design 2e Copyright 2 C2 M2 Y2 K 5

52 Representing Negtive Numbers: Two s Complement Negtive numbers common How represent in binry? Signed-mgnitude Use leftmost bit for sign bit So -5 would be: using four bits using eight bits Better wy: Two s complement Big dvntge: Allows us to perform subtrction using ddition Thus, only need dder component, no need for seprte subtrctor component Digitl Design 2e Copyright 2 52

53 Ten s Complement Before introducing two s complement, let s consider ten s complement But, be wre tht computers DO NOT USE TEN S COMPLEMENT. Introduced for intuition only. Complements for ech bse ten number shown to right. Complement is the number tht when dded results in Digitl Design 2e Copyright 2 53

54 Ten s Complement Nice feture of ten s complement Insted of subtrcting number, dding its complement results in nswer exctly too much So just drop the results in subtrcting using ddition only 2 complements Digitl Design 2e Copyright =3 7+6=3 3 Adding the complement results in n nswer tht is exctly too much dropping the tens column gives the right nswer. 54

55 Two s Complement is Esy to Compute: Just Invert Bits nd Add Hold on! Sure, dding the ten s complement chieves subtrction using ddition only But don t we hve to perform subtrction to hve determined the complement in the first plce? E.g., we only know tht the complement of 4 is 6 by subtrcting -4=6 in the first plce. True. But in binry, it turns out tht the two s complement cn be computed esily Two s complement of is, becuse + is Could compute complement of s = Esier method: Just invert ll the bits, nd dd The complement of is + =. It works! Q: Wht is the two s complement of? A: += (check: +=) Q: Wht is the two s complement of? A: += Digitl Design 2e Copyright 2 55

56 Two s Complement Two s complement cn represent negtive numbers Suppose hve 4 bits Positive numbers to 7: to Negtive numbers -: Tke two s complement of : + = -2: + = -: + = So - to -: to Leftmost bit indictes sign of number, known s sign bit. mens negtive. Signed vs. unsigned N-bit number Unsigned: to 2 N - Ex. Unsigned -bit: to 255 Signed (two s complement): -2 N- to 2 N- - Ex. Signed -bit: -2 to 27 Digitl Design 2e Copyright 2 Quick method to determine mgnitude of negtive number 4-bit: subtrct right 3 bits from. Ex. : -( 6) = -2 Or just tke two s complement gin: -(+) = - = -2 56

57 Two s Complement Subtrctor Built with n Adder Using two s complement A B = A + (-B) A B = A + (two s complement of B) = A + invert_bits(b) + N-bit So build subtrctor using dder by inverting B s bits, nd setting crry in to A Adder B cin S Digitl Design 2e Copyright 2 57

58 Adder/Subtrctor Adder/subtrctor: control input determines whether dd or subtrct Cn use 2x mux sub input psses either B or inverted B Alterntively, cn use XOR gtes if sub input is, B s bits pss through; if sub input is, XOR inverts B s bits A N-bit 2x A B Adder cin S B N-bit sub b7 b6 dder s B inputs sub Digitl Design 2e Copyright 2 5

59 Adder/Subtrctor Exmple: Clcultor Previous clcultor used seprte dder nd subtrctor Improve by using dder/subtrctor, nd two s complement numbers DIP swi tches clk f e sub DIP switches A B -bit dder/subtrctor S ld -bit register LEDs CALC A B -bit dder co S ci A B wi -bit subtrctor wo S Digitl Design 2e Copyright 2 clk f e ld 2x -bitregister LEDs CALC 59

60 Overflow Sometimes result cn t be represented with given number of bits Either too lrge mgnitude of positive or negtive Ex. 4-bit two s complement ddition of + (7+=). But 4-bit two s complement cn t represent number >7 + = WRONG nswer, in two s complement is -, not + Adder/subtrctor should indicte when overflow hs occurred, so result cn be discrded Digitl Design 2e Copyright 2 6

61 Detecting Overflow: Method For two s complement numbers, overflow occurs when the two numbers sign bits re the sme but differ from the result s sign bit If the two numbers sign bits re initilly different, overflow is impossible Adding positive nd negtive cn t exceed lrgest mgnitude positive or negtive Simple overflow detection circuit for 4-bit dder overflow = 3 b3 s3 + 3b3s3 Include overflow output bit on dder/subtrctor sign bits Digitl Design 2e Copyright 2 overflow () overflow (b) no overflow (c) If the numbers sign bits hve the sme vlue, which differs from the result s sign bit, overflow hs occurred. 6

62 Detecting Overflow: Method 2 Even simpler method: Detect difference between crry-in to sign bit nd crry-out from sign bit Yields simpler circuit: overflow = c3 xor c overflow () overflow (b) no overflow (c) If the crry into the sign bit column differs from the crry out of tht column, overflow hs occurred. Digitl Design 2e Copyright 2 62

63 Arithmetic-Logic Unit: ALU 4.7 ALU: Component tht cn perform vrious rithmetic (dd, subtrct, increment, etc.) nd logic (AND, OR, etc.) opertions, bsed on control inputs Digitl Design 2e Copyright 2 63

64 Multifunction Clcultor without n ALU Cn build using seprte components for ech opertion, nd muxes Too mny wires, lso wstes power computing opertions when only use one result t given time + DIP switches A B + AND OR XOR NOT Wsted power x s2 y -bit x s z s clk e Id -bit register A lot of wires CALC Digitl Design 2e Copyright 2 LEDs 64

65 ALU More efficient design uses ALU ALU design not just seprte components multiplexed (sme problem s previous slide) Insted, ALU design uses single dder, plus logic in front of dder s A nd B inputs Logic in front is clled n rithmetic-logic extender Extender modifies A nd B inputs so desired opertion ppers t output of the dder A B 7 b7 6 b6 b x y z AL-extender x y z AL-extender Digitl Design 2e Copyright 2 ALU IA IB Adder cin IS S () bext bext bext cinext i7 ib7 i6 ib6 i ib cin (b) 65

66 Arithmetic-Logic Extender in Front of ALU A B 7 b7 6 b6 b x y z AL-extender x y z AL-extender IA IB Adder cin IS ALU S () bext bext bext cinext i7 ib7 i6 ib6 i ib xyz= Wnt S=A+B : just pss to i, b to ib, nd set cin= xyz= Wnt S=A-B : pss to i, b to ib nd set cin= (two s complement) xyz= Wnt S=A+ : pss to i, set ib=, nd set cin= xyz= Wnt S=A : pss to i, set ib=, nd set cin= xyz= Wnt S=A AND B : set i=*b, b=, nd cin= Others: likewise Bsed on bove, crete logic for i(x,y,z,,b) nd ib(x,y,z,,b) for ech bext, nd crete logic for cin(x,y,z), to complete design of the AL-extender component (b) cin Digitl Design 2e Copyright 2 66

67 ALU Exmple: Multifunction Clcultor DIP swi tches A B + Ð + AND OR XOR NOT Wst ed pow er DIP switches x y s bit s z s e Id -bit regist er clk A lot of wi res. LEDs CALC Design using ALU is elegnt nd efficient No mss of wires No big wste of power clk x y z e A A x y z ld ALU S -bit register B B CALC LEDs Digitl Design 2e Copyright 2 67

68 Shifters Shifting (e.g., left shifting yields ) useful for: Mnipulting bits Converting seril dt to prllel (remember erlier bove-mirror disply exmple with shift registers) Multiply/divide by 2 (unsigned numbers only) Shift left once is sme s multiplying by 2. Ex: (3) becomes (6) Why? Essentilly ppending -- Note tht multiplying deciml number by ccomplished just be ppending, i.e., by shifting left (55 becomes 55) Shift right once sme s dividing by 2 i3 i2 i i 4. i3 i2 i i i3 i2 i i inr inl in in sh shl shr s s << Symbol Digitl Design 2e Copyright 2 q3 q2 q q Left shifter q3 q2 q q Shifter with left shift or no shift q3 q2 q q Shifter with left shift, right shift, nd no shift 6

69 Shifter Exmple: Temperture Averger Four registers storing history of tempertures Wnt to output the verge of those tempertures Add Use three dders Then divide by four Sme s shift right by 2 (7) () (2) (5) T clk ld R Rb Rc Rd ld shift in (42) divide by 4 >>2 () Note rounding Rvg ld Tvg Digitl Design 2e Copyright 2 69

70 Strength Reduction Mny multiplictions not by power of 2 constnts (2, 4,, ) E.g., by 5, or Could use multiplier component, but shifters re smll nd fst Replce multipliction by shifts nd dds Opertor strength reduction (multiply is stronger thn shift/dd) E.g., 5*C 4*C + C (4*C sme s C<<2) Replcing division by shifts nd dds slightly hrder Approximte frction using frction hving power of 2 denomintor E.g., C/5 =.2*C, pprox. equls (2/52)*C =.99*C (2/52)*C = C*( )/52 = (C*64 + C*32 + C*4+C*2)/52 = ((C<<6) + (C<<5) + (C<<2) + (C<<)) >> 9 Digitl Design 2e Copyright 2 7

71 Celsius to Fhrenheit Converter F = C*9/ F = C + C*4/ F = C + 4*(C*64+C*32+C*4+C*2)/ (/5 from prev. slide) F = C + (C*64+C*32+C*4+C*2)/2+32 C 6 <<6 <<5 <<2 << Note: Uses wider buses, pdded on the left, to void losing bits during shifts Determine biggest possible internl vlues, set width ccordingly Do divisions s lte s possible to reduce rounding errors + >>7 + 6 F = C +(C*64+C*32+C*4+C*2)/ Digitl Design 2e Copyright 2 7

72 Brrel Shifter i3 i2 i i A shifter tht cn shift by ny mount 4-bit brrel left shift cn shift left by,, 2, or 3 positions -bit brrel left shifter cn shift left by,, 2, 3, 4, 5, 6, or 7 positions (Shifting n -bit number by positions is pointless -- you just lose ll the bits) Could design using x muxes Too mny wires More elegnt design Chin three shifters: 4, 2, nd Cn chieve ny shift of..7 by enbling the correct combintion of those three shifters, i.e., shifts should sum to desired mount Digitl Design 2e Copyright 2 q3 q2 q q in sh Shift by shifter uses 2x muxes. x mux solution for -bit brrel shifter: too mny wires. Q: xyz=??? to shift by 5? x y z sh sh sh Net result: shift by 5: I <<4 in <<2 in << in Q 72

73 Counters nd Timers 4.9 N-bit up-counter: N-bit register tht cn increment (dd ) to its own vlue on ech clock cycle,,,,...,,, Count rolls over from to Terminl (lst) count, tc, equls during vlue just before rollover Internl design Register, incrementer, nd N-input AND gte to detect terminl count clr cnt tc 4-bit up-counter clr cnt clr Id tc 4-bit up-counter C bit register C + 4 Digitl Design 2e Copyright 2 73

74 Counter Exmple: Turnstile with Disply Count people pssing through turnstile Assume turnstile genertes -clock pulse on P Connect count to disply Button cn reset count Simple solution using upcounter reset from turnstile P clk clr cnt 32-bit up-counter tc unused Disply 32,46 Digitl Design 2e Copyright 2 74

75 Up/Down-Counter Cn count either up or down Includes both incrementer nd decrementer Use dir input to select, vi 2x mux: dir= mens up Likewise, dir selects pproprite terminl count vlue (ll s or ll s) dir clr cnt clr ld 4-bit up/down counter 2x tc 4-bit 2 x 4 4-bit register C Digitl Design 2e Copyright 2 75

76 Counter with Lod Up-counter tht cn be loded with externl vlue Designed using 2x mux. ld input selects incremented vlue or externl vlue Lod the internl register when loding externl vlue or when counting Note tht ld hs priority over cnt ld cnt clr Id clr tc L 4 4-bit 2x 4 4-bit register C + Digitl Design 2e Copyright 2 76

77 Counter with Prllel Lod Useful to crete pulses t specific multiples of clock Not just t N-bit counter s nturl wrp-round of 2 N Exmple: Pulse every 9 clock cycles Use 4-bit down-counter with prllel lod Set prllel lod input to () Use terminl count to relod When count reches, next cycle lods. Why lod nd not 9? Becuse is included in count sequence:, 7, 6, 5, 4, 3, 2,, 9 counts clk ld cnt tc 4 L 4-bit down-counter 4 C Digitl Design 2e Copyright 2 77

78 Counter Exmple: New Yer s Eve Countdown Disply Chpter 2 exmple previously used microprocessor to count from 59 down to in binry Cn use -bit (or 7- or 6-bit) down-counter insted, initilly loded with 59 Digitl Design 2e Copyright 2 59 L clk Hz ld clr cnt c c c2 c3 c4 c5 c6 c7 -bit downcounter tc i i i2 i3 i4 i5 6x64 dcd d d d2 d3 d5 d59 d6 d6 d62 d Hppy New Yer! fireworks Note: Use - bit counter, not 6-bit counter 7

79 Common Counter Use: Clock Divider Suppose hve 52 Hz oscilltor, but wnt 2 Hz pulse Thus, wnt divide fst clock by 256 Design using -bit upcounter, use tc output s pulse Counts from to 255 (256 counts), so pulses tc every 256 cycles cnt -bit up-counter tc C osc 52 MHz p (unused) 2 MHz Digitl Design 2e Copyright 2 79

80 Clock Division by Amount not Power of 2 Exmple: Hz Pulse Genertor from 6 Hz Clock Exmple: U.S. electricity stndrd uses 6 Hz signl Device my convert tht to Hz signl to count seconds Use 6-bit up-counter Up counter: Detected count of 59 clers counter to ; tc thus pulses every 6 cycles Note: Detect 59, not 6 (becuse the first number,, is included) Down counter pproch lso possible: When count reches, lod 59 clr osc 6 Hz cnt 6-bit up-counter tc C p osc 6 Hz ld cnt tc 6-bit down-counter C p unused Hz Hz Digitl Design 2e Copyright 2

81 Mesuring Time Between Events using n Up-Counter Initilly cler to. st event: Set cnt=. 2 nd event: Set cnt=. Then, multiply counted clock cycles by clock period to determine time Ex: Highwy speed mesurement system Two sensors nd b in rod Use FSM to detect becoming, set cnt=. Set cnt= when b If clock is khz (period is ms), then time is C *.s If nd b seprted by. miles, then vehicle speed in mph is:. miles / (time * ( hour / 36 seconds)) E.g., if C is 5, then speed is. / ((5*.) / 36) = 72 mph b Speed Mesurer vehicle b Speed Mesurer s S S S2 clr= cnt= cnt= (compute time nd output speed) b clr cnt C 6 Digitl Design 2e Copyright 2

82 Timers Pulses output t userspecified timer intervl when enbled Ticks like clock Intervl specified s multiple of bse time unit If bse is microsec nd user wnts pulse every 3 ms, lods 3, into timer Cn design using oscilltor, register, nd down-counter () Q (b) lod enble microsec oscilltor ld ld cnt (c) tc M Q bit register 4-bit 2x 32-bit down-counter 32 C unused M lod enble 32-bit -microsec Q timer Digitl Design 2e Copyright 2 2

83 Timer Exmple: Lser Surgery System Recll Chpt 3 lser surgery exmple Clock ws ns, wnted 3 ns, used 3 sttes. Wht if wnted 3 ms? Adding 3 million sttes is not resonble. Use timer Controller FSM lods timer, enbles, then wits for Q= Digitl Design 2e Copyright 2 Inputs: b, Q x= ld= en= x= ld= en= b Outputs:ld, en, x Off Strt (c) b' Q On b clk Q' x= ld= en= clk b Controller clk Inputs: b Q Stte Outputs: x ld en Off Lser Surgery System ns () ld en Q x (b) lser ptient 3, (in binry) M lod enble 32-bit microsec timer Q ms... Off Off Off Strt On... On... (d) Off x

84 Register Files 4. Accessing one of severl registers is: OK if just few registers Problemtic when mny Ex: Erlier bove-mirror disply, with 6 registers Much fnout (brnching of wire): Wekens signl Mny wires: Congestion Digitl Design 2e Copyright 2 C 4 lod lod C d d 4x62 4 d i i3-ii d2 e 32 d3 d5 e lod lod reg reg too much lodfnout reg lod reg2 lod lod reg3 reg5 T A I M bit registers tolerble 6 32-bit registers begins to hve fnout nd wire problems huge mux i i 32-bit -bit 6x 4 i d d DD 32 i2 congestion i5i3 s s s3-s x y 4 6*32 = 52 wires

85 Register File MxN register file: Efficient design for one-t--time write/red of mny registers Consider 6 32-bit registers Clled write port 32-bit dt to write 4-bit ddress specifies which register to write Enble (lod) line: Reg written on next clock 32 4 W_dt W_ddr W_en 6 32 register file R_dt R_ddr R_en bit dt tht is red 4-bit ddress to specifies which register to red Enble red red port Digitl Design 2e Copyright 2 5

86 Register File Internl design uses drivers nd bus d driver d q=d c q Boosts signl three-stte driver q 9 W_dt W_ddr W_en i i 2x4 32 d d d2 write decoder d3 e lod lod lod lod 4x32 register file reg reg reg2 reg bus driver R_dt d d d2 2x4 i i red decoder d3 e Internl design of 4x32 RF; 6x32 RF follows similrly R_ddr R_en c=: q=d d q c=: q= Z d q like no connection Note: Ech driver in figure ctully represents 32 -bit drivers Digitl Design 2e Copyright 2 6

87 Register File Timing Digrm Cn write one register nd red one register ech clock cycle My be sme register clk W_dt W_ddr W_en R_dt cycle cycle 2 cycle 3 cycle 4 cycle 5 cycle Z X X X X 2 3 Z Z 9 Z R_ddr X X 3 X 3 R_en 32 2 W_dt W_ddr R_dt R_ddr 32 2 : : 2: 3:???? : : 2: 3:??? 9 : : 2: 3:? 22? 9 : : 2: 3:? 22? 9 : : 2: 3:? 22? 9 : : 2: 3:? : : 2: 3:? W_en 4x32 register file R_en Digitl Design 2e Copyright 2 7

88 Register-File Exmple: Above-Mirror Disply 6 32-bit registers tht cn be written by cr s computer, nd displyed Use 6x32 register file Simple, elegnt design Register file hides complexity internlly And becuse only one register needs to be written nd/or red t time, internl design is simple C lod 4 i3-i e 32 d 4 6 d5 C WA lod lod lod reg 32too much fnout W_dt 4 W_ddr 32 OLD design W_en R_en d D 6x32 32 register file RA congestion reg5 huge mux 32 i bit D R_dt 6x 4 R_ddr i5 s3-s Digitl Design 2e Copyright 2

89 Chpter Summry Need dtpth components to store nd operte on multi-bit dt Also known s register-trnsfer-level (RTL) components Components introduced Registers Adders Comprtors Multipliers Subtrctors Arithmetic-Logic Units Shifters Counters nd Timers Register Files Next chpter combines knowledge of combintionl logic design, sequentil logic design, nd dtpth components, to build digitl circuits tht cn perform generl nd powerful computtions Digitl Design 2e Copyright 2 9