Concepts Introduced. A 1-Bit Logical Unit. 1-Bit Half Adder (cont.) 1-Bit Half Adder

Transcription

1 oncepts Introduced A -Bit Logicl Unit sic rithmetic/logic unit clocks ltches nd ip-ops registers SRAMs nd RAMs nite stte mchines Below is -it logicl unit tht performs AN nd OR opertions Both the AN nd OR opertions re lwys performed, ut the output produced depends on the selector to the multiplexor A 32-it logicl unit for AN nd OR opertions would just e n rry of these -it logicl units Opertion -Bit Hlf Adder A hlf dder tkes two inputs, nd, nd genertes two outputs, the crry nd the sum A hlf dder is clled (2,2) dder s it tkes two inputs nd produces two outputs Wht type of gte cn produce the crry output? Wht type of gte cn produce the sum output? Inputs Outputs crry sum omments + = 2 -Bit Hlf Adder (cont) The circuit for the crry cn use n AN gte The circuit for the sum cn use n XOR gte crry sum The gtes cn e comined together s one logic lock sum + = 2 + = 2 + = 2 crry

2 -Bit Full Adder Only the lest signicnt its (LSBs) will use hlf dder The ddition for the other its need third input, which is the from the previous it position This type is clled full dder or (3,2) dder since it tkes three inputs nd produces two outputs -Bit Full Adder (cont) Note the crryout nd the sum outputs for the full dder dier from the hlf dder Sum = = Inputs Outputs Sum omments + + = two + + = two + + = two + Sum + + = two + + = two + + = two + + = two + + = two Sum from Full Adder from Full Adder Sum = = = + + Sum

3 from Full Adder (cont) Sum nd from Full Adder = + + Sum Hrdwre ely -Bit ALU for AN, OR, nd Addition This -it ALU performs AN, OR, nd ddition on nd Opertion ely is dened s the time from when the input is stle to the time when the output is stle Will the full -it dder dely e greter thn the hlf -it dder dely? 2

4 32-Bit ALU for AN, OR, nd Addition Supporting Sutrction The 32-it dder, lso clled the ripple crry dder, is creted y linking the of the previous -it dder to the of the current -it dder Fster dders re possile 2 2 ALU ALU ALU2 Opertion 2 Rememer tht = + = + + in two's complement representtion So to support : Invert every it in Add to the result Add with 3 3 ALU3 3 -Bit ALU for AN, OR, Addition, nd Sutrction This -it ALU performs AN, OR, nd ddition on ( nd ) or ( nd ) By selecting nd setting to in the LSB of the ALU, the ALU cn perform sutrction of from Binvert Opertion -Bit ALU for AN, OR, NOR, Addition, nd Sutrction This -it ALU performs AN, OR, nd ddition on ( or ) nd ( or ) By selecting nd, ( NOR ) is produced from ( AN ) Ainvert Binvert Opertion 2 2

5 Supporting the SLT Instruction eling with Overow Rememer tht the slt instruction produces if rs < rt (or < ) nd otherwise So we need to set ll ut the lest signicnt it (LSB) to The LSB is set ccording to the result of the most signicnt it (MSB) fter performing n - opertion ( ) < (( ) + ) < ( + ) < When the result of the sutrction is greter thn the lrgest positive representle vlue or is smller thn the smllest negtive representle vlue, then we hve n overow The MSB of sutrction result cnnot e used when there is n overow A+B Opernd A Opernd B Overflow? < < < < < < Yes No < < No < No < < No < No hecking for Overow hecking for Overow (cont) We cn detect overow y checking if the nd of the MSB dier The lrgest positive vlue is Adding the two lrgest positive vlues will give result of, which hs the MSB set, ut the is not set The smllest negtive vlue is Adding the two smllest negtive vlues will give result of, which hs the MSB cler, ut the is set MSB MSB rry In MSB MSB rry rry MSB Over- XOR A B In Out flow? rry Out Notes No Yes crries differ No A < B No A > B No A > B No A < B Yes crries differ No

6 -Bit ALU for All Bits Except the Most Signicnt Bit This -it ALU hs n extr input clled tht cn e used for the result of the slt instruction This -it ALU is used for ll its except the MSB Ainvert Binvert Opertion 2 3 -Bit ALU for the Most Signicnt Bit This -it ALU for the MSB hs n output clled Set for the slt instruction from performing the sutrction This -it ALU lso checks for overow Ainvert Opertion Binvert Set Overflow detection Overflow Ainvert Opertion Binvert 32-Bit ALU for AN, OR, NOR, Addition, Sutrction, SLT Supporting the BE Instruction The Set output is the input for the LSB -it ALU A zero is input s the signl for ll other -it ALUs If Overow is set, then the Set result for the MSB should e inverted Binvert Ainvert Overflow detection 2 ALU 3 ALU Set Opertion Overflow To support eq instruction, we cn get the result of nd check if the result is zero ( = ) = To check if ny of the sutrction it results re not zero: NotZero = ( ) 2 2 ALU2 2 To check if ll of the sutrction it results re zero: Zero = ( ) ALU3 Set Overflow

7 Finl 32-Bit ALU The Zero result is used for the eq instruction Ainvert Bnegte 2 2 ALU ALU ALU2 2 Opertion ALU3 Set Overflow Zero ALU ontrol Lines The ALU control lines cn e represented s inry vlue The MSB is the Ainvert line, the 2nd MSB is the Binvert line, nd the two LSBs re the Opertion lines ( - AN, - OR, - dd, - slt) ALU control lines AN OR dd Function sutrct set on less thn NOR Universl ALU Symol Below is the universl symol tht is used to represent complete ALU ALU opertion Verilog Behviorl enition of MIPS ALU module MIPSALU(ALUctl, A, B, ALUOut, Zero); input [3:] ALUctl; input [3:] A, B; output reg [3:] ALUOut; output Zero; ALU Zero Overflow ssign Zero = (ALUOut == ); A, B) cse (ALUctl) : ALUOut <= A & B; : ALUOut <= A B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B? : ; 2: ALUOut <= ~(A B); defult: ALUOut <= ; endcse endmodule

8 locks Stte Elements A clock is signl tht ocsilltes etween low nd high voltges in xed period of time The clock cycle time or clock period is the time etween two trnsitions from low voltge to high voltge (rising edges) or the time etween two trnsitions from high voltge to low voltge (flling edges) Edge-triggered clocking mens ll stte chnges occur on the ctive (rising or flling) clock edge Flling edge A stte element hs some type of internl storge nd t lest two inputs nd one output The required inputs to stte element re the dt vlue to e written nd the clock signl, which indictes when the dt vlue is to e written The output from stte element is the vlue tht ws written on previous cycle Some stte elements re only written when there is n explicit write signl is ctive lock period Rising edge Synchronous System A signl is vlid when it is stle (not chnging) nd the vlue will not chnge gin until the inputs chnge A synchronous system is logic system tht employs clocks nd dt signls re red only when the clock indictes tht the signl vlues re stle (not chnging) In synchonous system, stte elements provide inputs to comintionl logic lock nd the outputs of the comintionl logic re stored in stte elements, which occurs only on the ctive clock edge Reding nd Writing the Sme Stte Element It is possile to hve stte element tht is used s oth n input nd output to the sme comintionl lock Stte element omintionl logic Stte element omintionl logic Stte element 2 lock cycle

9 A Verilog Speciction of lock Ltches nd Flip-Flops A clock cn e specied in Verilog s register tht is updted on ech time step reg clock; // clock is register lwys egin # clock = ; # clock = ; end Ltches nd Flip-ops re the simplest stte elements The dierence is the point t which the clock cuses the stte to chnge In clocked ltch, the stte cn chnge when the clock signl is sserted nd in ip-op, the stte is chnged only on n ctive clock edge Unclocked S-R Ltch Unclocked S-R Ltch Actions Below is n S-R ltch (set-reset ltch), which is uilt from pir of NOR gtes S stnds for set the stte to, R stnds reset the stte to, is the output, nd is the complement of the output When neither S nd R re sserted, retins its previous stte When S is sserted nd R is desserted, then is set to When S is desserted nd R is sserted, then is reset to Asserting oth S nd R is not llowed R S Inputs Initil Stle R S =R NOR =S NOR =R NOR =S NOR Action = NOR = NOR = NOR = NOR hold stte of = NOR = NOR = NOR = NOR hold stte of = NOR = NOR = NOR = NOR set to = NOR = NOR = NOR = NOR set to = NOR = NOR = NOR = NOR reset to = NOR = NOR = NOR = NOR reset to not llowed not llowed

10 Ltch Opertion of Ltch A ltch hs two inputs, which re the dt vlue () to e stored nd the clock signl () tht indictes when the ltch should red the input nd store it A ltch hs two outputs, which re the internl stte () nd its complement () When is sserted, the ltch is sid to e open nd when is desserted, then ltch is sid to e closed When the (clock) signl is sserted, then the ltch is open nd the output ssumes the vlue of the input A Flip-Flop with Flling-Edge Trigger Opertion of Flip-Flop with Flling-Edge Trigger A ip-op's stte only chnges on clock edge The gure elow shows how flling-edge ip-op is constructed from pir of ltches When flls, the rst ltch (mster) is closed nd the second ltch (slve) is open nd gets its input from the mster ltch When the (clock) signl chnges from sserted to desserted, then the output ssumes the vlue of the input ltch ltch

11 Verilog Behviorl escription of Flip-Flop The posedge indictes tht the lwys construct is only reevluted when the clock chnges from to Register Files A register le cn e implemented s n rry of registers uilt from ip-ops, where ech register requires 32 ip-ops Typiclly register le hs t lest two red ports nd one write port module FF(clock,,, r) input clock, ; output reg ; output r; ssign r = ~; clock) = ; endmodule Red register numer Red register numer 2 Write register Write dt Register file Write Red dt Red dt 2 Register File Red Ports Register File Write Port Register le red ports for n registers re implemented with pir of n-to- multiplexors The register numer is used s the multiplexor selector signl Red register numer Red register numer 2 Register Register Register n 2 Register n M u x M u x Red dt Red dt 2 A register le write port is implemented using decoder tht tkes the register numer s input to determine which register to write Both the decoder output nd write signl hve to e set for register to e written The register vlue to e written is third input

12 Register File Write Port (cont) MIPS Register File Written in Behviorl Verilog Write The register le is only written on the positive edge of the clock when the RegWrite signl is set Register numer n-to-2 n decoder n 2 n Register Register module registerfile(red, Red2, WriteReg, Writet, RegWrite, t, t2, clock); input [5:] Red, Red2, WriteReg; input [3:] Writet; input RegWrite, clock; output [3:] t, t2; reg [3:] RF [3:]; Register dt Register n 2 Register n ssign t = RF[Red]; ssign t2 = RF[Red2]; clock) if (RegWrite) RF[WriteReg] <= Writedt; endmodule SRAM RAM SRAM - Sttic Rndom Access Memory Used in cches Usully hs single ccess port tht cn provide either red or write ccess Requires 6 trnsistors per it to prevent dt from eing corrupted when red nd requires 4 times the mount of spce s compred to RAM for ech stored it Ech it vlue is stored in cell y using pir of inverting gtes nd the vlue cn e kept indenitely s long s power is pplied, which is why SRAM is clled sttic SRAM ssess time is out 5 to times fster thn RAM SRAM is perhps 2 times more expensive thn RAM Synchronous SRAM (SSRAM) hs synchronous interfce to llow urst trnsfers, where clock is used to trnsfer successive words given only strting ddress nd length RAM - ynmic Rndom Access Memory Used for min memory Requires single trnsistor per it, which is lost fter eing red, so ech red requires tht the dt e written ck The vlue representing it is kept in cell tht is stored s chrge in cpcitor tht is ccessed y the single trnsistor RAM requires tht the dt e refreshed periodiclly, out 5% of the cycles, which is why RAM is clled dynmic nd is ccomplished y reding the dt nd writing it ck

13 RAM Accesses RAM Optimiztions Access time - time etween when red is requested nd the desired word rrives ycle time - minimum time etween requests to memory The ddress pins to RAM chip re typiclly decresed y two y multiplexing the ddress lines Row Access Stroe (RAS) - rst hlf of the ddress is sent for the row olumn Access Stroe (AS) - second hlf of the ddress is sent for the column RAMs llow repeted ccesses to the sme row without nother RAS, which is clled fst pge mode Synchronous RAM (SRAM) dds clock signl to void overhed of synchronizing with the memory controller nd llows vrile numer of ytes to e sent over multiple cycles per memory request oule dt rte (R) trnsfers dt on oth the rising nd flling edges of the RAM clock signl SRAMs introduced 2 to 8 nks tht cn operte independently nd simultneously service independent requests, which lso reduces power SRAMs hve low power mode, which disles the SRAM except for the internl refresh Returning to n ctive power mode requires out 2 cycles Error etection ode Hmming Error orrection ode Most memories use n error-checking code to detect possile corruption of dt With prity code, the numer of its tht re s in word is counted nd prity it is stored indicting if the numer of dt its is odd () or even () When the word is red, then the prity it is red nd if the prity of the word does not mtch the prity it, then n error is detected Use of single prity it provides single it error detection code A Hmming code llows detection nd correction of it of error Steps to clculte the Hmming error correction code (E) Numer its from left to right strting from esignte ll it positions tht re powers of 2 s prity its nd ll other its s dt its The position of the prity it determines the sequence of dt its tht it checks Bit checks its (, 3, 5, 7, 9, ) where the rightmost it ssocited with the vlue is Bit 2 checks its (2, 3, 6, 7,, ) where the second rightmost it ssocited with the vlue is Bit 4 checks its (4-7, 2-5, 2-23, ) where the third rightmost it ssocited with the vlue is Bit 8 checks its (8-5, 24-3, 4-47, ) where the fourth rightmost it ssocited with the vlue is Set prity its to crete even prity for ech group

14 Hmming E for Eight t Bits Single error correction (SE) requires p prity its for d dt its, where p >= log2(p + d + ) So p=4 when d=8, p=5 when d=6, p=6 when d=32, etc Ech dt it is covered y two or more prity its If the vlue of the four prity clcultions indictes ll even prity, then there is no error Otherwise, the it pttern of the prity its indictes which it is in error Bit position Encoded dt its Prity it coverge p p2 p4 p p p2 d p4 d2 d3 d4 p8 d5 d6 d7 d8 X X X X X X X X X X X X X X X X X X X X X X Exmple of Using Hmming E for Eight t Bits Assume one yte dt vlue is Leving spces for the prity its, the 2-it pttern would e Filling in the prity its, the 2-it pttern would e Assume it ten is in error, so the dt word would e Prity it is (), which is OK since 4 one's re set Prity it 2 is (), which hs n error since 5 one's re set Prity it 4 is (), which is OK since 2 one's re set Prity it 8 is (), which hs n error since 3 one's re set Prity its 2 nd 8 detect errors, so it (2+8) must e wrong nd the error cn e corrected y inverting tht it Single Error orrecting / oule Error etecting odes Finite Stte Mchines With n dditionl prity it tht is clculted over the entire word, single it errors cn e corrected nd doule it errors cn e detected Assume 4-it word, so the old positions in re the prity its, where H is the originl prity its (p, p2, nd p3) nd p4 is prity it for the entire word There re four cses when t most two its cn e in error H nd p4 oth indicte no error, so no error occurred H nd p4 oth indicte n error, so correctle single error occurred s p4 indictes the sme error s H H indictes no error nd p4 indictes n error, so single error occurred in the p4 it, ut not in the rest of the word H indictes n error nd p4 indictes no error, so doule error occurred s p4 clcultes even prity if two errors occurred SE/E codes re commonly used in min memories tody The ehvior of sequentil systems depends on oth the inputs nd the contents of internl memory nd nite stte mchines (FSMs) re used to descrie their ehvior A nite stte mchine consists of: set of sttes A next-stte function tht given the current stte nd current inputs determines the next stte An output function tht produces set of outputs from the current stte nd inputs

15 Finite Stte Mchines (cont) Intelligent Trc ontroller Prolem esign FSM to control green nd red trc light t the intersection of north-south rod nd est-west rod Inputs urrent stte lock Next-stte function Output function Next stte Outputs two output signls: NSlite: When this signl is sserted, the light on the north-south rod is green; when desserted it is red EWlite: When this signl is sserted, the light on the est-west rod is green; when desserted it is red two input signls: NScr: Indictes there is t lest one cr over the detectors plced in the roded in the north-south rod EWcr: Indictes there is t lest one cr over the detectors plced in the roded in the est-west rod The trc light should chnge from one direction to the other if there is cr witing in the other direction; otherwise the light should continue to e green in the sme direction Intelligent Trc ontroller Prolem (cont) Intelligent Trc ontroller Prolem (cont) Below is the next stte function depicted in tle Need two sttes NSgreen: The trc light is green in the north-south direction EWgreen: The trc light is green in the est-west direction Below is grphicl representtion of the nite stte mchine EWcr NSgreen: NSlite NScr EWcr EWgreen: EWlite NScr urrent Stte Inputs NScr EWcr Next Stte NSgreen NSgreen EWgreen NSgreen EWgreen EWgreen EWgreen EWgreen NSgreen NSgreen Below is the output function for ech stte depicted in tle urrent Stte Outputs NSlite EWlite NSgreen EWgreen

16 Implementing Finite Stte Mchine Implementing the Intelligent Trc ontroller A FSM is implemented with stte register tht holds the current stte nd comintionl logic lock to compute the next stte nd the outputs omintionl logic Outputs Next stte The vlue in the stte register indictes the current stte We need to ssign numers to identify the sttes Assign to NSgreen Assign to EWgreen We only need it register since there re only two sttes Stte register Inputs Implementing the Intelligent Trc ontroller (cont) Implementing the Intelligent Trc ontroller (cont) Below is the sme tle for the next stte function using stte numers insted of nmes urrent Stte NScr Inputs EWcr Next Stte This tle cn e expressed s the following logic eqution Below is the sme tle for the output function using stte numers insted of nmes urrent Stte NSlite Outputs EWlite This tle cn e expressed s the following logic equtions NSlite = urrentstte EWlite = urrentstte NextStte = (urrentstte EWcr) + (urrentstte NScr)

17 Implementing the Intelligent Trc ontroller (cont) Verilog Version of the Trc Light ontroller NSlite EWlite NScr module TrfficLite(EWcr, NSr, EWLite, NSLite, clock); input EWcr, NScr, clock; output EWlite, NSlite; reg stte; lock flip flop it stte EWcr initil stte = ; ssign NSLite = ~stte; ssign EWLite = stte; clock) cse (stte) : stte = EWr; : stte = NSr; endcse endmodule Four Steps to Build Finite Stte Mchine Step : etermine the stte trnsitions hoose n initil stte Represent the stte trnsitions with grph nd tle Step 2: stte ssignment Assign unique numer to ech stte Rewrite the stte trnsition tle to use the ssigned stte numers Step 3: Produce the comintionl logic equtions Step 4: Implement the equtions in hrdwre