ELECTRICAL TESTING OF A CMOS BASELINE PROCESS. by David Rodriguez. Memorandum No. UCB/ERL M94/63 30 August 1994

Transcription

1 ELECTRICAL TESTING OF A CMOS BASELINE PROCESS by David Rodriguez Memorandum No. UCB/ERL M94/63 30 August 1994 ELECTRONICS RESEARCH LABORATORY College of Engineering University of California, Berkeley CA 94720

2 TABLE OF CONTENTS Chapter 1 Introduction Background and Motivation Approach Thesis Organization Chapter 2 Types of Electrical Test Structures Test Structures for Device Characterization Test Structures for Process Characterization Test Structures for Capturing Catastrophic Faults Test Structures for Reliability Analysis Test Structures for Circuit Characterization Chapter 3 Test Structure Design Test Structures for Device Characterization Individual MOSFETs x 4 MOSFET Arrays Capacitors Test Structures for Process Characterization Contact Resistors Split Cross Bridge Resistors Fallon Ladder Self-aligned n+ Bridges Catastrophic Fault and Reliability Analysis Contact Chains Comb Resistors Serpentine/Comb Resistors Serpentines Over Topography MOSFET With Antenna Chapter 4 Test Chip Organization Scribe Lane Drop-In Die Complete Test Chip Chapter 5 Automated Testing System Introduction Using Sunbase die.map prober.text Measurement Subroutines Sample Run

3 TABLE OF CONTENTS (cont.) Chapter 6 Sample Results and Analyses Introduction Resolution Tests Analysis of the Split-Cross-Bridge Resistor Conclusion Chapter 7 Conclusion References Appendix I Appendix II LIST OF TABLES Table 1: Labels Used For Test Structure Layers Table 2: Sample Data from Metal 1 to N-Diff., 3µm x 3µm Cross-Contact Chains.. 17 Table 3: Split-Cross-Bridge Resistors Included in BCAM Design Table 4: Sample Measured Data from Polysilicon, Split-Cross-Bridge Resistor Table 5: Sample Measurement Data from Fabricated, Polysilicon Fallon Ladders Table 6: Sample Extracted Results of Polysilicon-to-N+ Misalignment Table 7: Sample Measured Values for Serpentines With and Without Topography.. 40 Table 8: Test Structures for Device Characterization Table 9: Test Structures for Process Characterization Table 10:Test Structures for Catastrophic Faults and Reliability Analysis Table 11:Currently Available Measurement Subroutines for Autoprober Table 12:Percent Error as a Function of Voltage Measured, 100 Replications

4 LIST OF FIGURES Figure 1 Configuration of standard pad set used for all electrical, DC measurements Figure 2 One subset of individually probed MOSFETs Figure 3 Close view of 4x4 array. Metal 2 connects drains in each row Figure 4 4 x 4 NMOS array within pad set. (W/L) = 20/2) Figure 5 300µm x 300µm oxide capacitors between substrate and well Figure 6 Four terminal contact resistor Figure 7 Cross contact resistor chain Figure 8 Unchained contact resistors used for small contact sizes Figure 9 Split-Cross-Bridge Resistor in polysilicon with 2µm line width and spacing Figure 10 Cross-bridge resistor used for n+ diff. layer. P+ diff. cross-bridge is similar Figure 11 Fallon Ladders, used for determining minimum resolvable line width Figure 12 Results from Fallon Ladder experiment showing linear relationship Figure 13 Self aligned n+ bridges to test misalignment between poly and nitride Figure 14 Model of self-aligned n+ bridge Figure 15 Metal 1 to n+ diffusion contact chains. Five chains are included per pad set Figure 16 Comb resistor used to monitor spot defects Figure 17 Serpentine/Comb structure for defect monitoring Figure 18 Metal 1 serpentine with no topography, used for metal step coverage analysis...39 Figure 19 Metal 1 serpentine over topography Figure 20 MOSFETs used for evaluation of gate oxide damage due to plasma process Figure 21 Die configuration and labelling of a 4 inch wafer used in the baseline process...43 Figure 22 Configuration of scribe lane and drop-in die within the stepper field Figure 23 Arrangement of test structures within scribe lane Figure 24 Configuration of test structures within the drop-in area Figure 25 Complete scribe lane and drop-in area, showing location of structures Figure 26 Hardware and software configuration of autoprobing system Figure 27 Trend plot showing voltage resolution for a measured voltage of V Figure 28 Trend plot showing 300 measured R S results a single polysilicon cross-bridge..66 Figure 29 Scatter plot of linewidth versus R S for wafer 1. (ρ =0.63) Figure 30 Wafer contour map of sheet resistance values on wafer Figure 31 Wafer contour map of linewidth values on wafer Figure 32 Illustration showing that increased poly line thickness increases linewidth Figure 33 Wafer contour map of sheet resistance values on wafer Figure 34 Wafer contour map of linewidth values on wafer

5 Acknowledgments I would like to express my sincere gratitude to my research advisor, Professor Costas J. Spanos, for his valuable research guidance and continued support of my goals. I am also extremely grateful to Professor Jan Rabaey for his insightful comments during the review of this thesis, and to Loren Linholm for sharing his knowledge of characterizing lithography systems. Many thanks are extended to Eric Boskin, whose patience and guidance proved invaluable from the outset of this research. Likewise, I am indebted to Crid Yu for his time and effort in sharing his knowledge of statistical analysis and characterization, particularly in the domain of lithography and etch performance. For his continued efforts in the cooperative design of the measurement software for these test structures, I am grateful to Vadim Gutnik. For answering my many FrameMaker and processing questions, I thank Sherry Lee, Tony Miranda and Shenqing Fang. Many thanks are also extended to Raymond Chen, Sean Cunningham, Zeina Daoud, Mark Hatzilambrou, Shang-Yi Ma and Pamela Tsai. These and the rest of the persons mentioned in these acknowledgments have provided a very open and supportive environment throughout my stay here. Finally, I would like to extend special thanks to my friends and family who have unconditionally supported me in my endeavors, in particular my wife-to-be, April Hachenburg, whose support and love has made this achievement and my happiness possible.

6 Chapter 1 Introduction 1.1 Background and Motivation Over the years, the minimum feature size of typical CMOS integrated circuits has been decreasing at a rapid pace. This has lead to increasingly dense, complex circuits. The complexity of these product circuits makes them virtually useless for monitoring or debugging a fabrication process. As a result, ancillary test devices are often fabricated along with a product. These devices, or test structures, are measured in a much more timely manner to yield specific information regarding either the product circuit or the fabrication process. This information can then be used to predict circuit performance and yield, to monitor and control a process, or to provide debugging information when a process yields unacceptable results. The devices are often placed in the scribe lanes of a wafer, which are those areas between die that are later cut through to separate the die. For a more complete characterization, test structures are also included in the area between the scribe lanes. This use of test structures is of particular interest to the Berkeley Computer-Aided Manufacturing (BCAM) group. In particular, an effort is underway to maintain a baseline process in the Berkeley Microfabrication Laboratory. This facility services research customers with a wide range of needs and recipes. As a result, careful attention must be paid to providing some form of control to the process. This control comes in the form of a baseline process run monthly. Test structures fabricated during this baseline run, along with scribe-lane test structures manufactured alongside product circuits, will be measured and the resulting data will be statistically analyzed. Analysis results will be used to determine whether or not the process is in control, and if not what particular part of the process needs attention.

7 Although the primary use of the test structures will initially come in the form of monitoring the baseline process, a broader use of the test chip is expected. The structures lend themselves well to use in other BCAM areas of emphasis, such as performance and yield prediction, and modeling the manufacturability of circuit designs. As the research in these areas mature, the set of test structures proposed in this project will be available for process and device characterization. 1.2 Approach The first step taken in designing the test structures was to survey currently used structures in both production and in research and development environments [4]-[15]. This provided an understanding of the various types of structures used, as well as the important issues in test structure design. The needs of the BCAM test chip were identified, and an appropriate set of test structures was designed and fabricated. Details of the layout and fabrication of the structures were determined with regard to the particular characterization required, along with adherence to certain standards defined for ease of probing. Furthermore, particular attention was paid to the organization of the test chip as a whole, especially with regard to the scribe lane. Software routines were written and organized within an automated probing system to further ease data gathering. The system was used to collect the characterization data, and the data was in turn verified against expected test structure results. 1.3 Thesis Organization The work described in this document can be divided into four parts. The first part, described in Chapter 2, includes the survey of test structures and their various applications. Details of the structure designs chosen, including motivation for the structure s use and verification results, are presented in Chapter 3. The third part, organization of the scribe lane and test chip as a whole, is described in Chapter 4. The automated probing system and accompanying software is described in Chapter 5, with a sample results and analyses following in Chapter 6. Finally, a conclusion is included in Chapter 7.

8 Chapter 2 Types of Electrical Test Structures Test structures are used for a variety of purposes in the fabrication of integrated circuits. Test structures are used for device, circuit and process parameter extraction, as well as random fault and reliability testing. These five categories will be described in further detail in this chapter. 2.1 Test Structures for Device Characterization Device parameters are those used to model devices for circuit simulation purposes. The most obvious example of such parameters are those that are used by SPICE to model transistor operation. One of two approaches may be taken when extracting device parameters. The first approach, direct parameter extraction, concentrates on designing test structures and parameter extraction routines such that a parameter can be extracted independently from the influence of other parameters. Contrary to extracting device parameters individually, the optimization method of parameter extraction involves collecting a general set of data representing all parameters. The device model s various parameters are then fitted to the measurements by an optimization routine, such that the extracted parameters can be used by the model to reproduce the measured data during simulation. The choice of using direct extraction versus optimization is one which involves a number of trade-offs, and considerable time should be spent in studying this issue. For this reason, test structures for device parameter extraction, namely MOSFETs and capacitors, where designed such that either method could be used. The method of parameter extraction is then left to the user.

9 2.2 Test Structures for Process Characterization In semiconductor fabrication considerable emphasis is placed on the spatial uniformity, adherence to specifications, and lot to lot consistency of parameters which define a process. Monitoring process parameters such as doping concentration, contact and sheet resistance, critical dimension, oxide thickness, etc., play a key role in maintaining a process under control. Measurements can be performed either optically or electrically. As the name suggests, optical measurements make use of optical information in extracting parameters, such as the width of a polysilicon line. Electrical measurements, on the other hand, make use of probing equipment to force a set of electrical inputs to the structure, and to measure the response. The test structure is designed such that according to basic electrical principles, the measured response can be translated to a single process parameter. Note that great care must be taken in designing the device, such that measurements depend on a single process parameter. Although optical measurements are at times more accurate and revealing, their use is rather time consuming relative to automated, electrical measurements. As stated previously, one of the primary uses for these test structures will be to collect statistical information about a process. This necessitates a reasonably large set of measurements be performed in a short amount of time. It is for this reason that the primary emphasis of this thesis concerns electrical measurements. 2.3 Test Structures for Capturing Catastrophic Faults The lack of uniformity in processing across a stepper field and wafer, and the impurity of the fabrication process often lead to the introduction of physical faults on a wafer. These faults come in a variety of forms, but generally result in loss of function prior to significant stressing of affected devices. Several examples of defects contributing to random faults are: breaks in metal lines due to the interaction of a contaminating particle and photoresist, shorts in metal lines caused by solid particles deposited on metal layers, oxide pinhole defects, and broken lines due to insufficient metal step coverage. Test structures were designed to electrically determine if shorting

10 or breaking of metal lines appear on a wafer, and if so provide the approximate defect location for visual inspection, if desired. 2.4 Test Structures for Reliability Analysis Reliability failures are those which occur after a significant amount of stress is placed on the structures of interest. This stress can come in a variety of forms, including overvoltage, current density, temperature, humidity, and radiation. The subsequent failure results from atomic motion or changes in ionic charge states [1]. As an example, consider perhaps the simplest and most common occurrence of reliability failure, electromigration. Electromigration is defined as the displacement of metal ions through a conductor resulting from the passage of direct current. This shift is caused by a modification of the normally random diffusion process to a directional one caused by charged carriers [2]. The greatest concern of electromigration is that over time sections of metal wire carrying a high current density become thinner, and eventually disconnect. A simple reliability test would then consist of stressing a long, thin metal line with a high current density over some time and checking for an open circuit. Additional failures which may occur due to other forms of stressing include dielectric breakdown, charge injection, and corrosion [1]. In most cases, these failures can be monitored by stressing structures used for device and process parameter extraction and reliability failure. For this reason, separate structures used exclusively for reliability failure analysis were not necessary, except for the case of monitoring oxide damage due to plasma etching. Therefore, random fault and reliability structures were included in the same category of test structure design in Chapter Test Structures for Circuit Characterization Circuit parameters are those which characterize the performance of a complete integrated circuit (IC). A subset of such parameters are maximum operating frequency, average power dissipa-

11 tion, and drive capability. Since measuring these parameters from the product circuit is usually much too complex and time intensive, special test structures that mimic the behavior of the IC are introduced. These test structures, however, yield values which may be difficult to relate directly to some processing step. Nonetheless, they provide a reasonable estimate of the expected performance of the product circuit. A common example of the type of test structure used to characterize an integrated circuit is the ring oscillator. Measuring the oscillation frequency of ring oscillators can provide a reasonable frequency range within which the process can be expected to provide functional product circuits. It is obvious that test structures for circuit parameter extraction are fairly dependent on the product circuits to be characterized. Since the concern of this project was broader in scope than a specific circuit, test structures for circuit parameter extraction were not built. However, those structures designed for device parameter extraction can be used, along with circuit simulation, in order to obtain an estimate of a circuit s performance on the process of interest.

12 Chapter 3 Test Structure Design This chapter provides the details concerning individual test structure design. In particular, each section will contain a general description of the test structure and its usage, along with design details and measured results. This chapter is organized according to the types of test structures defined in Chapter 2. Note, however, that as mentioned in the previous chapter test structures for characterizing ICs are not included, and structures used for reliability and catastrophic fault analysis are combined since they differ only in measurement technique. Of particular interest to the BCAM group is characterizing a 2µm CMOS n-well process, this being the minimum size reliable device that can be produced by the CMOS baseline. Furthermore the process provides two metal layers, metal 1 and metal 2, with design rule metal linewidth and pitch of 3µm and 6µm, respectively, on each layer. Design rules for contacts require 3µm x3µm contact cuts. All test structures described here can be easily scaled to accommodate finer features when they become available. Common to all electrically measurable test structures designed is the array of pads used for probing. Each pad is a 100µmx100µm square of metal 2 over metal 1, with the appropriate vias. Ten pads are placed in a 2x5 array, with all pad spacings set to 100µm, in order to form the set of pads contacted with each drop of the probes onto the wafer. See Figure 1 for an example of the 2x5 pad set. The pad labels refer to the numbering scheme used by the autoprober, which is discussed further in Chapter 5. All test structures were labelled in polysilicon, metal 1 and metal 2, to aid in locating structures when using a microscope. Labels were made as large as possible within the 100µm spacing between pads, given approximately 20µm spacing between the labels and the

13 1 100µm µm µm 100µm Figure 1 Configuration of standard pad set used for all electrical, DC measurements. pads. The layers of the n-well, CMOS process are labelled as listed in Table 1. Furthermore, all numeric labels have units of microns, unless otherwise labelled. Finally, tables in this chapter which list measured data contain columns labelled die X and die Y, which refer to the integer coordinates of the die within the wafer. Die configuration within the wafer will be discussed in detail in Chapter 4, but can be previewed by studying Figure 21. Table 1 : Labels Used For Test Structure Layers Label layer Label layer PO polysilicon NW n-well N+ n+ diffusion M1 metal 1 P+ p+ diffusion M2 metal Test Structures for Device Characterization Individual MOSFETs The primary objective of device characterization is to extract enough physical information for modeling the electrical behavior of a transistor. Therefore, the prominent test structure in this category is the basic transistor. As mentioned previously, decisions concerning the specifics of device parameter extraction have been left for the potential users of these structures. Nonetheless, an attempt has been made to provide a thorough set of structures to be used for that research.

14 Based on our 2µm CMOS process, and on device requirements for existing methods of direct parameter extraction and parameter optimization, a number of transistors were included. The transistor set consists of devices with drawn gate lengths of 1, 1.3, 1.5, 2, 3, 5, 10 and 25 µm. For each length listed, both an NMOS and a PMOS device of drawn width of 5, 10 and 50 µm were included. Each pad set can be used to individually probe three devices, each with the same gate length but a different width, resulting in a total of 16 pad sets. With the exception of the body contact, there are no common terminals for any of these devices, in order to eliminate problems associated with parasitic leakage currents distorting results when probing a single device. The devices may be redesigned to share terminals if further research determines that this would not pose a problem. The layout of one subset of MOSFETs is shown in Figure x 4 MOSFET Arrays Integrated circuit designers, particularly in the analog domain, often require electrically matched device parameters in a very localized area. In order to measure electrical device mismatch, tightly coupled arrays of transistors were designed and fabricated. Both PMOS and NMOS transistors arrays have been included. Source Gate Source Gate Source Drain Gate Drain Bulk Drain Figure 2 One subset of individually probed MOSFETs.

15 Figure 3 shows the MOSFET array in detail. Each transistor has a gate length of 2µm and a width of 10µm, with 5µm horizontal spacing and 15µm vertical spacing between source and drain regions of nearby transistors. All gates share a common lead while each of the remaining pads connects to four transistor sources or drains. Transistor drains are connected vertically via metal 2 connections, and share a common leads labelled D1, D2, D3 and D4, where the numbers 1 through 4 represent the array column number from left to right. Similarly, common sources are connected horizontally in metal 1, labelled S1, S2, S3 and S4, where the numbers 1 through 4 represent the array row number from top to bottom. Probing a single transistor within the array is accomplished by contacting and applying inputs to the appropriate source and drain leads, while leaving the other leads floating. As a simple example, consider collecting data for an I DS -V GS curve on the transistor in the lower right corner of the array, at V DS set to 5V. The first step would be to apply a ground to lead S4, and a voltage of 5V onto lead D4. The gate lead is appropriately swept in voltage while current readings are taken Gate D 1 D 2 S 2 D 3 Figure 3 S 3 D 4 S 4 S 1 Close view of 4x4 array. Metal 2 connects drains in each row.

16 Gate D 1 D 2 D 3 D 4 Bulk S 1 S 2 S 3 S 4 Figure 4 4 x 4 NMOS array within pad set. (W/L) = 20/2) between D4 and S4. All of the transistors in the array can be measured in a similar fashion, by simply asserting the appropriate source and drain leads. Finally, Figure 4 shows the NMOS array within a pad set. The leads shown in Figure 3 are simply connected to pads, with an additional pad available as a contact to the substrate or well. The label NA indicates that the device is an NMOS array, while label 20/2 indicates that the transistors have gate lengths of 20µm and widths of 2µm Capacitors The final set of test structures included for device parameter extraction consists of two large capacitors, illustrated in Figure 5. Capacitors have been reliably used for some time in character- Figure 5 300µm x 300µm oxide capacitors between substrate and well.

17 izing gate oxide. Two 300µm x300µm capacitors have been included to perform this characterization. Frequency dependent C-V measurements can be applied to these capacitors to extract gate oxide thickness and analyze oxide integrity by monitoring trapped charge, oxide to substrate interface charge, and mobile ions in the oxide itself. These high-frequency measurement techniques fall outside the realm of the DC measurement techniques emphasized in this thesis, and as such will not be discussed here. Note that this structure has pads of 100µm x 100µm, which are spaced 100µm apart. However, this is the only structure which does not adhere to the standard 2x5 pad set. 3.2 Test Structures for Process Characterization Contact Resistors Previous studies have found that in a well-controlled CMOS process, contact resistance has a relatively large percentage variation [4]. This variation is not of great concern assuming that contact resistance is substantially less than a transistor s on resistance. However, sustained advances in manufacturing are resulting in smaller and thus more resistive contacts. The variation of contact resistance is then of growing concern, as contact resistance approaches that of a transistor s on resistance. The basic structures used in the evaluation of contacts are contact chains and 4 terminal and 6 terminal contact resistors. Contact chains do not isolate the variability of the contacts themselves, and are therefore left for catastrophic fault analysis, to be discussed later. Contact resistors, however, are used to measure the interfacial resistance, or the resistance between the layers being contacted, as well as misalignment between the masks used to form the contact. The choice of using 4 versus 6 terminal contacts was a trade off between complexity of design and probing, and granularity of results. For a better understanding of this trade off, consider the true, interfacial resistance, R I, with respect to measured resistance, R K, and a factor called flange resistance, R F [5]. Note in the four

18 terminal contact resistor in Figure 6 that the voltage and current taps of the contact resistor are wider than the contact. This is necessary in order to account for misalignment between each layer and the contact cut. A simple Kelvin measurement [17] will result in a resistance higher than that of the true interfacial resistance, due to the parasitic current flow in the voltage taps. The flange resistance is a measure of this additional resistance. The following equations describe this relationship: R K = (V 1 -V 2 )/I, (1) and R K = R I + R F. (2) The problem of extracting R I and R F from (2) from perfectly aligned contacts has been solved by what is known as the Thin-Film Model [5], which uses heuristics to predict the flange effect resistance. In a later study, Lieneweg and Sayah [6] propose a similar method of extracting R I from misaligned four and six terminal contacts. The method includes procedures for estimating the actual misalignment in both horizontal, x, and vertical, y, directions. According to the study, four terminal contacts provide for the extraction of the average of two contacts interfacial resistance, and can also calculate the sum of the x and y misalignment components. Six terminal contacts isolate the x and y misalignment components and provide a single interfacial resistance. Finally, Lieneweg and Sayah state that R F can be treated as constant across a wafer, and R Kavg, V 1 I I V 2 Figure 6 Four terminal contact resistor.

19 I in V 1 V 3 V 4 V 5 V 2 left V 4 right V 6 V 8 contact contact GND Figure 7 Cross contact resistor chain. the average of a right and left contact, then reflects the variation of R I. Left and right contacts simply differ in the position of the contact relative to the voltage taps. Figure 7 illustrates the two types of contact in a cross contact resistor chain. Note that the left contact has its n+ diffusion voltage tap extending upward, where n+ diffusion is illustrated by a darker line, and the right contact has its n+ diffusion voltage tap extending downward. Therefore, any vertical misalignment would draw the contact closer to one of the n+ diffusion voltage taps, but further from the other, causing a difference in voltage readings and therefore in resistance measurements. A drawback of using six terminal contacts is that they cannot be chained as efficiently as four terminal contacts. Furthermore, they need an entire pad set per contact and require about twice as many measurements. Since the primary concern here is that of process control, the ability to accurately monitor contact resistance variation with four terminal contacts made it the test structure of choice. Using the four terminal contact also allowed for faster data collection by including four contacts per pad set. Figure 7 shows the final test structure design. The label CR indicates that the test structure is a cross-contact resistor chain. Labels M1, N+ and 2 indicate that contacts are between metal 1 and n-diffusion, and are 2µm on each side of the contact cut. The contact chains designed include both 2µm and3µm contacts between metal 1 and metal 2, n- diffusion, p-diffusion and polysilicon. Smaller contacts were also included to test the limits of the

20 process, but were not chained in order to save area. See Figure 8 for an example of how these contacts are placed in a pad set. This smaller contact set contains 1.5µm contacts between metal 1 and n-diffusion, p-diffusion and poly, and 2.5 µm contacts between metal 1 and metal 2. The labels in Figure 8 indicate that the contact on the left is between metal 1 and polysilicon, and is 1.5µm on each side. Similarly, the contact on the right is between metal 1 and metal 2 and is 2.5µm on each side. Taking contact resistance measurements on the cross-contact chain of Figure 7 is rather straightforward. Simply supply a current, I, which passes from pad I in through the ground pad, and measure the voltage between the voltage taps of each contact. Measurement error is introduced into equation (1) due to the resolution limit of voltage and current measurement units used during probing. Error is introduced to the contact resistance by both a voltage measurement resolution limit, V, and a current measurement resolution limit, I. These limits for the equipment used are described in more detail in section 6.2 of this report. Of these two resolution limits, only that of voltage measurements was found to be a significant contributor to resistance measurements, and was found to be 0.1mV. The following analysis calculates the measurement error for contact resistance measurements. Using equation (1) as a basis, then: I in V 1 I in V 1 V 2 GND V 2 GND Figure 8 Unchained contact resistors used for small contact sizes.

21 and R K = R K V I = R K V V I, (3). (4) As an example, consider contact resistance measurements taken with a test current of I=3mA. Assuming that the resulting voltage measurements were approximately 1V in magnitude, then V = (0.01%)*1V = 0.1mV. The expected resolution of contact resistance measurements is: R K 0.1mV = = 0.033Ω 3mA. (5) Table 2 lists sample data from six die. The columns R Lavg and R Ravg represent the average of the two left and two right contacts, respectively, in a single n+ diffusion to metal 1cross-contact resistor chain. The columns labeled die X and die Y contain the x and y integer coordinates of the die within the wafer, and R avg is the average of R Lavg and R Ravg. Table 2 : Sample Measurement Data from Metal 1 to N-Diffusion, 3µm x 3µm Cross- Contact Chains. die X die Y R Lavg (Ω) R Ravg (Ω) R avg (Ω) Split Cross Bridge Resistors Monitoring sheet resistance and linewidth variation are of great concern in semiconductor manufacturing. Sheet resistance is a direct reflection of the resistivity of interconnect, which can produce undesirable effects on the performance of CMOS circuits due to unwanted voltage drops

22 and RC delay. It is also a direct measure of the doping process, which can effect a great deal of CMOS parameters, from source and drain contact resistance to threshold voltage. Linewidth variation has perhaps an even greater influence on circuit performance because it defines channel length, and therefore current drive capability of CMOS devices. Furthermore, the minimum allowable pitch of interconnect influences the overall size of a fabricated circuit, since it often dictates the area required by the routing channels in a circuit. A single test structure can be used to measure sheet resistance, linewidth, and line pitch for a particular layer. This structure, the split-cross-bridge-resistor [8]-[10], is shown in Figure 9. The measurements are divided into three distinct sections. The cross part of the structure is used to perform the sheet resistance measurement, R S, using the very well established van der Pauw relation [7]: Rs = π V 1 V ln2 I RS, (6) where I R is the current flowing from pad I 1 through pad I 2. The middle part of the structure, the bridge resistor, is used to measure linewidth variation. Given the measured value of sheet resistance, the linewidth of the bridge, W b, is calculated from the relationship: W b = R S L b I b V b, (7) V 1 V 2 V 6 V 7 I 3 L b L S(top) LS(bot) I 1 I 2 V 3 V 4 V 5 Cross (R s ) Bridge (W b ) Split-Bridge (W s, Pitch) Figure 9 Split-Cross-Bridge Resistor in polysilicon with 2µm line width and spacing.

23 where L b is the length between voltage pad V 2 and pad V 3 of the bridge resistor, I b is the current flowing from pad I 1 through pad I 3, and V b is the voltage (V 3 -V 2 ). Note that the line length will also vary from its designed value, but the variation is negligible as compared to the considerably long drawn length. Finally, the width of the thinner, split-bridge elements are measured in a similar manner: and R S L I S ( top ) b ( ) = W S top W S bot 2V S( top) R S L I S ( bot ) b ( ) = V S( bot), (8), (9) where W S(top),L S(top) and W S(bot),L S(bot) are the widths of the split-bridges and lengths between voltage taps, of the top and bottom split-bridges, respectively. Similarly, V S(top) and V S(bot) are the voltages (V 4 -V 5 ) and (V 6 -V 7 ), respectively. The factor of two in the denominator is based on the assumption that current is divided equally between the top and bottom split-bridges. Finally, the spacing, S, and pitch, P, are calculated from measured data: S = W b W Stop ( ) W S( bot), (10) and P = W S S( top) + W S( bot) 2. (11) Obviously, the dimensions of the bridge resistors are of considerable importance when extracting parameters. Table 3 lists the split-cross-bridge resistors designed, along with specifics about the bridge resistor dimensions. Note that those cross-bridges made in diffusion, illustrated in Figure 10, do not contain a split-bridge but rather an elongated middle bridge, since pitch is not a concern for diffusion. The elongated bridge further reduces any error introduced into (7) from variation in line length.

24 Table 3 : Split-Cross-Bridge Resistors Included in BCAM Design Layer W b (µm) L b (µm) W S(top,bot) (µm) L S(top) (µm) L S(bot) (µm) S (µm) Polysilicon Metal Metal n+ diffusion N/A N/A N/A N/A p+ diffusion N/A N/A N/A N/A Labels on the resistors, in order from left to right, refer to layer, split-bridge drawn width in microns, and split-bridge drawn spacing in microns. The drawn bridge width is simply: W b(drawn) = 2*W S(drawn) + S (drawn), (12) where W S(drawn) is the drawn width of both the top and bottom split bridges. For example, the structure shown in Figure 9 is a polysilicon split-cross-bridge resistor with W S(drawn) =2µm, S (drawn) =2µm, and W B(drawn) =6µm. The labels for cross-bridges with no split consist of the layer name first, followed by the bridge width to the right. Therefore, Figure 10 is labeled as a n+ diffusion cross-bridge with drawn width of 4.5µm. The electrical measurement technique for the cross-bridge and split-cross-bridge resistors follows the analysis described previously. First, the values necessary to calculate R S are measured by V 1 V 2 I 3 I 1 I 2 V 3 Figure 10 Cross-bridge resistor used for n+ diff. layer. P+ diff. cross-bridge is similar.

25 passing a current from pad I 1 to pad I 2, while the voltages at pads V 1 and V 2 are measured. For line width calculations, the current is directed from pad I 1 to pad I 3, and voltages at pads V 2 through V 7 are measured for the split-cross-bridge pictured in Figure 9, or voltages at pads V 2 and V 3 are measured for the cross-bridge pictured in Figure 10. Measurement error is introduced by both a voltage measurement resolution limit, V, and a current measurement resolution limit, I. Of these two resolution limits, only the voltage measurement was considered to be a significant contributor to resistance measurements. The following analysis calculates the measurement error for the various extracted parameters for the splitcross-bridge resistor. First, consider the sheet resistance measurement, R S. Starting with the sheet resistance, equation (6), the error is calculated as follows: R S = V I R R S V 1, (13) and R S = V π I R ln2. (14) For the W b measurement: and W b V W b W = R b S V R S, (15) W b = L b I b R S V + R V b V S b. (16) Similarly, for the W S(top) and W S(bot) measurements: L S( top, bot) I S( top, bot) W S( top, bot) = V S( top, bot) R S V + R S V S( top, bot). (17) The form of this equation differs from that of W b by the factor of 2 in the denominator, which is due to only half of the bridge current passing through each element of the split-bridge. The error in the measurement of spacing, S, by differentiating equation (10):

26 and S = W S b W S Stop ( ) W S bot W b W S( top) S ( ) W S( bot) S = W + b W + Stop ( ) W W 2 W S( bot) = + b S top, bot ( ) (18). (19) Finally, for the pitch measurement, P, of equation (11): and P = S P + W P S( top) W S bot S W Stop ( ) P ( ) W S( bot) 1 P = S + -- W 2 S top + -- W 2 S( bot) = S + W S top, bot ( ) 1 ( ) (20). (21) Table 4 lists sample data collected from polysilicon, split-cross-bridge resistors, identical in drawn dimensions to the structure in Figure 9. The data was collected from six separate die, all on the same wafer. Table 4 : Sample Measured Data from Polysilicon, Split-Cross-Bridge Resistor die X die Y R S (Ω/ ) W b drawn (µm) W b meas. (µm) W s drawn (µm) W sbot meas. (µm) W stop meas. (µm) S (µm) P (µm) Fallon Ladder While cross-bridge resistors are used to measure line width variation, they do so only at a given drawn width. It is also desirable to assess the lithography and etching capability of a process

27 by determining the minimum resolvable line width. Testing this with cross-bridge resistors would require a large number of structures, and therefore considerable die area. M. Fallon and A.J. Walton [11] recently proposed an electrical test structure to determine the minimum resolvable line width that can be resolved by a process, given a relatively small die area. The design of this structure, the Fallon ladder, is based on calculated step changes in resistance that occur when a line is not resolved. Figure 11 shows the implementation of the Fallon ladders used for the BCAM test chip. Each rung of each ladder is 0.1µm smaller than the previous rung, when traversing the ladder from right to left. Furthermore, the resistance of the rails between each pair of rungs is kept constant by making all rails the same length and width. Resistance measurements are taken on the ladders by passing a current from pad I through pad GND, and measuring the voltage difference between pads V 1 and V 2. The premise of using this ladder structure is that each rung of the ladder, if resolved, will decrease the total resistance by some incremental amount. A linear function then exists between measured resistance and minimum resolved line width.

28 I V 1 I V 1 GND V 2 GND V 2 I V 1 I V 1 GND V 2 GND V 2 Figure 11 Fallon Ladders, used for determining minimum resolvable line width. The bottom two ladders of Figure 11 are used to calibrate this function. The left and right ladders are drawn with minimum rung widths of 3.3µm and 3.7µm, respectively. Assuming that the process can reliably resolve at least a 3.3µm metal line, resistance measurements on both ladders provide the data necessary to determine the linear function relating minimum line width resolved and resistance measured. Note that the top two ladders have minimum rung widths of 1.4µm, although the process is only expected to reliably resolve 3µm lines. Given the calibrated function, and a resistance measurement on one of the top ladders in Figure 11, the line width of the smallest rung resolved on that ladder can now be determined. This technique was verified on the 2µm CMOS process at Berkeley, using polysilicon ladders. Rather than the minimum set of ladders, 24 ladders were included, each with a different number of rungs. Starting with a ladder which had a minimum rung width of 2.7µm, each ladder had an additional rung which was 0.1µm narrower than the minimum rung width of the previous ladder. The ladder with the most rungs had a minimum rung width of 0.4µm. A plot of resistance mea-

29 surements taken on these ladders, versus their minimum drawn rung width, should then show the linearity in the relationship. Figure 12 illustrates the results of the experiment, which show that indeed a linear relationship holds. Note that for very small rung widths, namely 0.4µm and 0.5µm, the resistance no longer drops as with the ladders with larger sized minimum rungs. This shows that 0.6µm was the last line width resolved. Given the successful verification of the Fallon ladder on our process, the test structure as shown in Figure 11 could now be included on the test die. First, the linear function, lw meas = slope R meas + b, (22) is calibrated with the following equations: slope = R 1 R lw1 drawn lw0 drawn, (23) and b = R 0 slope lw0 drawn, (24) where R 1 and R 0 are resistances measured from the calibration ladders, with minimum drawn Resistance (Ω) lines smaller than 0.6µm were not resolved drawn line width of smallest ladder rung Figure 12 Results from Fallon Ladder experiment showing linear relationship.

30 rung widths of lw1 drawn and lw0 drawn, respectively. Now, the ladder complete with all rung widths is measured, yielding the value R meas, which can be used in conjunction with equations (22)-(24) to find the minimum linewidth resolved, lw meas. Measurement error again results from the limitations in voltage and current measurement. As before, the error due to the current measurement s resolution limit is considered negligible. The expected error for resistance measurements, R, is first calculated by considering the following resistance equation, based on two voltage measurements: where Therefore, and R R R = V , I (25) V 1,2 = V 1 -V 2. (26) = V R I V 12, V = ( 1) = I V I, (27). (28) Now, considering equations (22)-(24), the error in linewidth measurement, lw meas, can be calculated as follows: where slope = R slope R 10,, (29) R 1,0 = R 1 - R 0. (30) and slope = R lw1 drawn lw0 drawn. (31) substituting (28) into (31) and simplifying: slope = V (32) I( lw1 drawn lw0 drawn )

31 A similar analysis yields the expected error for b: and b = R b slope b , (33) R 0 slope b = R 0 + lw0 drawn ( slope). (34) The expected measurement error on minimum rung width resolved can now be calculated from (22) as follows: and lw meas slope lw meas lw R meas meas slope b = lwmeas b R meas lw meas = R meas slope + slope R meas + b (35). (36) Fallon ladders were designed for polysilicon, metal 1, and metal 2 layers. As shown in Figure 11, the set of test structures for each layer consists of two calibration ladders, occupying one pad set, and two characterization ladders, occupying another pad set. Note that in the calibration pad set there is a metal line extending between the top and bottom, rightmost pads of the set. This line has the width of the most narrow calibration rung. A continuity check should be performed on this line to ensure that the process can resolve the line widths necessary for the calibration. The labels on the top of each pad set describe the test structure, and the layer characterized. The labels along the bottom of the pad sets describe the minimum, and maximum rung widths drawn. For example, in the bottom pad set of Figure 9, the labels FL, M1, 3.3 and 4.0 refer to a Fallon Ladder in metal 1, with minimum rung width of 3.3µm and maximum rung width of 4.0µm. Table 5 lists the results of resolution measurements taken on polysilicon Fallon ladders. The data was collected from six separate die, all on a single wafer.

32 Table 5 : Sample Measurement Data from Fabricated, Polysilicon Fallon Ladders die X die Y lw0 drawn (µm) R 0 (Ω) lw1 drawn (µm) R 1 (Ω) lw2 meas. (µm) R 2 (Ω) lw3 meas (µm) R 3 (Ω) Self-aligned n+ Bridges Another limiting factor in the shrinking of fabrication processes is the misalignment between the various layers of integrated circuits. The accuracy and precision of overlaying these successive patterns is often monitored optically. These structures provide early feedback in the process, but are often costly or time consuming. An electrical test structure has been included in the BCAM test chip to provide a quick, low cost, post-processing assessment of the misalignment between polysilicon and active area. The structure is based on using the polysilicon gate of a transistor to separate the source and drain regions in a self-aligned process. The structure is designed as two, very wide transistors, with a short polysilicon gate perfectly centered over each active area region, as illustrated in Figure 13. The gate is left unconnected, and serves to create two long, thin resistors per transistor. Depending on the amount and direction of misalignment during fabrication, the resistors will vary in width, and thus in resistance.