CMOS INVERTER LAYOUT TUTORIAL

Size: px
Start display at page:

Download "CMOS INVERTER LAYOUT TUTORIAL"

Transcription

1 PRINCESS SUMAYA UNIVERSITY FOR TECHNOLOGY CMOS INVERTER LAYOUT TUTORIAL

2 We will start the inverter by drawing a PMOS. The first step is to draw a poly layer. Click on draw a rectangle and choose the poly layer PO from the right side pane. Use the ruler to get a poly rectangle of width= 0.1 um, and a length about 1 um as shown in the figure below. The second step is to draw a diffusion region. Draw a diffusion rectangle (DIFF) with a width of 0.48 um and a length of 0.9 um. Place the diffusion rectangle in the center of the diffusion area, that is, the diffusion area should be placed 0.4 um to the left and 0.4 um to the right of the POLY. The figure below shows the diffusion area placed. Place the diffusion area about in the middle of the poly as seen.

3 The next step will be placing a PIMP area. Place the area over the diffusion area having a margin area of 0.14 um taken from every corner as below. Each PMOS transistor should have an N-WELL base layer. Add a new N-WELL layer on your design. Take a 0.1 um margin from the bottom line. Stretch the N-WELL layer as seen below using the stretch tool found in the left toolbar. We will use this area in a couple of steps ahead.

4 Now add a metal area by choosing M1 from the right panel. The metal contact should be placed at 0.05 um from the right side of the diffusion and have a width of 0.23 um as seen below. Stretch the metal area down. Until now, your design should look like this

5 In the same manner add a new metal area on the left side and stretch it up as follow. Now place four contacts in the diffusion area as seen below. The contact should be at least 0.45 um away from the metal borders.

6 Now add a square NIMP area at the edge of the metal that you stretched upwards. Align the NIMP area to the PIMP rectangle as seen below. Add a diffusion area inside the NIMP square. And as before, take a 0.14 um margin from all the corners to place a diffusion area like this.

7 Now place a contact in the diffusion area as seen below. The contact should be placed as before, that is at least 0.45 um from the metal borders. This contact represents the source of the PMOS. You are almost done of designing the layout of your first PMOS. The design until now should look familiar as this one.

8 Now add a metal pin M1PIN on the source contact. Then press q on your keyboard and change the pin s name to the same name you used for your supply, for example AVDD. The pin should be placed over the contact as seen below. Now back to the original CMOS inverter circuit. As seen from the circuit, both gates of the NMOS and PMOS transistors Are connected together to form the input of the inverter. The gate of the MOS transistor is the POLY rectangle that we placed first. Thus the POLY of the PMOS will be stretched to meet the POLY of the NMOS and the PMOS drain which is represented by the metal rectangle that we stretched down should be in touch with the NMOS drain as seen from the circuit.

9 Stretch the POLY rectangle and add a place for a contact the will later represent the input pin as seen in the figure below. Now add a metal rectangle with the same size (0.21 um x 0.3 um) and this will represent the base of the input contact. After that add a contact using the same dimensions rules that we used earlier. Add an M1PIN over the contact and rename it to IN. This is the inverter s input signal.

10 After this, create the NMOS using the same steps that we used for the PMOS but with the following differences: 1- The Diffusion area s width is half that for the PMOS, that is 0.24 um. 2- Replacing the PIMP area with a NIMP area using the same margin rules. 3- No N-WELL layer surrounds the NMOS. The design should look like the one below. After that, start designing the source of the NMOS which will eventually be the contact at which the ground 0 volts is connected. This is achieved by drawing a 0.6 um x 0.6 um PIMP rectangle in which we place a 0.33 um x 0.33 um diffusion area. A contact along with an M1PIN called AVSS are placed using the same previous scheme. The design should look similar to this.

11 Now you have your complete design of your first inverter. But there is still one step to go. We need to define the output of out inverter. To do that, add an M1PIN on the common metal area between the two transistors. The M1PIN need not to be placed over a contact. Name the pin as the name you used in your schematic, for example OUT.

12 Here it is. Your complete layout design for your CMOS inverter. Verify your connections using the DRC test and then proceed with your simulations.

TUTORIAL II ECE 555 / 755 Updated on September 11 th 2006 CADENCE LAYOUT AND PARASITIC EXTRACTION

TUTORIAL II ECE 555 / 755 Updated on September 11 th 2006 CADENCE LAYOUT AND PARASITIC EXTRACTION TUTORIAL II ECE 555 / 755 Updated on September 11 th 2006 CADENCE LAYOUT AND PARASITIC EXTRACTION After finishing a schematic of your design (Tutorial-I), the next step is creating masks which are for

More information

Design rule illustrations for the AMI C5N process can be found at:

Design rule illustrations for the AMI C5N process can be found at: Cadence Tutorial B: Layout, DRC, Extraction, and LVS Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Revised by C Young & Waqar A Qureshi -FS08 Document Contents Introduction

More information

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #1, Full Custom VLSI (inverter layout)

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #1, Full Custom VLSI (inverter layout) CPE/EE 427, CPE 527, VLSI Design I: Tutorial #1, Full Custom VLSI (inverter layout) Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville Adapted from Virginia Tech, Dept.

More information

VLSI Lab Tutorial 3. Virtuoso Layout Editing Introduction

VLSI Lab Tutorial 3. Virtuoso Layout Editing Introduction VLSI Lab Tutorial 3 Virtuoso Layout Editing Introduction 1.0 Introduction The purpose of this lab tutorial is to guide you through the design process in creating a custom IC layout for your CMOS inverter

More information

UNIVERSITY OF WATERLOO

UNIVERSITY OF WATERLOO UNIVERSITY OF WATERLOO UW ASIC DESIGN TEAM: Cadence Tutorial Description: Part I: Layout & DRC of a CMOS inverter. Part II: Extraction & LVS of a CMOS inverter. Part III: Post-Layout Simulation. The Cadence

More information

EE 330 Spring 2018 Laboratory 2: Basic Boolean Circuits

EE 330 Spring 2018 Laboratory 2: Basic Boolean Circuits EE 330 Spring 2018 Laboratory 2: Basic Boolean Circuits Contents Objective:... 2 Part 1: Introduction... 2 Part 2 Simulation of a CMOS Inverter... 3 Part 2.1 Attaching technology information... 3 Part

More information

Layout and Layout Verification. of an Inverter Circuit

Layout and Layout Verification. of an Inverter Circuit Layout and Layout Verification of an Inverter Circuit Santa Clara University Department of Electrical Engineering By Piyush Panwar Under Guidance of Dr Samiha Mourad Date of Last Revision: August 7, 2010

More information

EE 330 Laboratory 3 Layout, DRC, and LVS Fall 2015

EE 330 Laboratory 3 Layout, DRC, and LVS Fall 2015 EE 330 Laboratory 3 Layout, DRC, and LVS Fall 2015 Contents Objective:... 2 Part 1 Creating a layout... 2 1.1 Run DRC Early and Often... 2 1.2 Create N active and connect the transistors... 3 1.3 Vias...

More information

FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT

FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT DIC1: Schematic Design Entry, Simulation & Verification DIC2: Schematic Driven Layout Drawing (SDL) Design Rule Check (DRC)

More information

Virtuoso Layout Editor

Virtuoso Layout Editor This tutorial will cover the basic steps involved in using the Cadence layout editor called Virtuoso, extracting layout, and running simulation on the layout. The inverter layout is used as an example

More information

ELEC451 Integrated Circuit Engineering Using Cadence's Virtuoso Layout Editing Tool

ELEC451 Integrated Circuit Engineering Using Cadence's Virtuoso Layout Editing Tool ELEC451 Integrated Circuit Engineering Using Cadence's Virtuoso Layout Editing Tool Contents Contents 1. General 2. Creating and Working On a Layout o 2.1 Undoing/Re-doing an Action o 2.2 Display Options

More information

Cadence Tutorial 2: Layout, DRC/LVS and Circuit Simulation with Extracted Parasitics

Cadence Tutorial 2: Layout, DRC/LVS and Circuit Simulation with Extracted Parasitics Cadence Tutorial 2: Layout, DRC/LVS and Circuit Simulation with Extracted Parasitics Introduction This tutorial describes how to generate a mask layout in the Cadence Virtuoso Layout Editor. Use of DIVA

More information

Lab 2. Standard Cell layout.

Lab 2. Standard Cell layout. Lab 2. Standard Cell layout. The purpose of this lab is to demonstrate CMOS-standard cell design. Use the lab instructions and the cadence manual (http://www.es.lth.se/ugradcourses/cadsys/cadence.html)

More information

EE 330 Laboratory 3 Layout, DRC, and LVS

EE 330 Laboratory 3 Layout, DRC, and LVS EE 330 Laboratory 3 Layout, DRC, and LVS Spring 2018 Contents Objective:... 2 Part 1 creating a layout... 2 1.1 Run DRC... 2 1.2 Stick Diagram to Physical Layer... 3 1.3 Bulk Connections... 3 1.4 Pins...

More information

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2019 HW5: Delay and Layout Sunday, February 17th Due: Friday,

More information

ECE471/571 Energy Efficient VLSI Design Project 2 Cadence Setup and Creation of an Inverter Due Date 11:30 am on Friday, February 2 nd, 2018

ECE471/571 Energy Efficient VLSI Design Project 2 Cadence Setup and Creation of an Inverter Due Date 11:30 am on Friday, February 2 nd, 2018 ECE471/571 Energy Efficient VLSI Design Project 2 Cadence Setup and Creation of an Inverter Due Date 11:30 am on Friday, February 2 nd, 2018 Introduction This project will first walk you through the setup

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Lab #2: Layout and Simulation

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Lab #2: Layout and Simulation UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Lab #2: Layout and Simulation NTU IC541CA 1 Assumed Knowledge This lab assumes use of the Electric

More information

EEC 116 Fall 2011 Lab #1 Cadence Schematic Capture and Layout Tutorial

EEC 116 Fall 2011 Lab #1 Cadence Schematic Capture and Layout Tutorial EEC 116 Fall 2011 Lab #1 Cadence Schematic Capture and Layout Tutorial Dept. of Electrical and Computer Engineering University of California, Davis September 26, 2011 Reading: Rabaey Chapters 1, 2, A,

More information

Virtuoso Schematic Composer

Virtuoso Schematic Composer is a schematic design tool from Cadence. In this tutorial you will learn how to put electrical components, make wire connections, insert pins and check for connection error. Start Cadence Custom IC Design

More information

Cadence Virtuoso Schematic Design and Circuit Simulation Tutorial

Cadence Virtuoso Schematic Design and Circuit Simulation Tutorial Cadence Virtuoso Schematic Design and Circuit Simulation Tutorial Introduction This tutorial is an introduction to schematic capture and circuit simulation for ENGN1600 using Cadence Virtuoso. These courses

More information

Spiral 2-8. Cell Layout

Spiral 2-8. Cell Layout 2-8.1 Spiral 2-8 Cell Layout 2-8.2 Learning Outcomes I understand how a digital circuit is composed of layers of materials forming transistors and wires I understand how each layer is expressed as geometric

More information

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group.

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group. Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group. Revision Notes: Aug. 2003 update and edit A. Mason add intro/revision/contents

More information

Select the technology library: NCSU_TechLib_ami06, then press OK.

Select the technology library: NCSU_TechLib_ami06, then press OK. ECE 126 Inverter Tutorial: Schematic & Symbol Creation Created for GWU by Anis Nurashikin Nordin & Thomas Farmer Tutorial adapted from: http://www.ee.ttu.edu/ee/cadence/commondirectory/final%20tutorials/digitalcircuitsimulationusingvirtuoso.doc

More information

Art of Layout Euler s path and stick diagram. Kunal Ghosh

Art of Layout Euler s path and stick diagram. Kunal Ghosh Art of Layout Euler s path and stick diagram Kunal Ghosh I wrote about Euler s path and stick diagram in two different blogs, but now is the time to show you how are they connected. It s simple and, seems,

More information

EECE 285 VLSI Design. Cadence Tutorial EECE 285 VLSI. By: Kevin Dick Co-author: Jeff Kauppila Co-author: Dr. Arthur Witulski

EECE 285 VLSI Design. Cadence Tutorial EECE 285 VLSI. By: Kevin Dick Co-author: Jeff Kauppila Co-author: Dr. Arthur Witulski Cadence Tutorial EECE 285 VLSI By: Kevin Dick Co-author: Jeff Kauppila Co-author: Dr. Arthur Witulski 1 Table of Contents Purpose of Cadence 1) The Purpose of Cadence pg. 4 Linux 1) The Purpose of Linux

More information

Fall 2008: EE5323 VLSI Design I using Cadence

Fall 2008: EE5323 VLSI Design I using Cadence 1 of 23 9/17/2008 6:47 PM Fall 2008: EE5323 VLSI Design I using Cadence This tutorial has been adapted from EE5323 offered in Fall 2007. Thanks to Jie Gu, Prof. Chris Kim and Satish Sivaswamy of the University

More information

EE115C Digital Electronic Circuits. Tutorial 4: Schematic-driven Layout (Virtuoso XL)

EE115C Digital Electronic Circuits. Tutorial 4: Schematic-driven Layout (Virtuoso XL) EE115C Digital Electronic Circuits Tutorial 4: Schematic-driven Layout (Virtuoso XL) This tutorial will demonstrate schematic-driven layout on the example of a 2-input NAND gate. Simple Layout (that won

More information

Logging in, starting a shell tool, and starting the Cadence Tool Suite

Logging in, starting a shell tool, and starting the Cadence Tool Suite EEE 4134 VLSI I Laboratory Lab 0 (Introductory Lab) Logging into Cadence Server, Tool Setup, Cell Library Creation, Introduction to Custom IC Design flow Objectives: To login, start a shell tool and start

More information

ANALOG MICROELECTRONICS ( A)

ANALOG MICROELECTRONICS ( A) ANALOG MICROELECTRONICS (304-534A) IBM 130 nm CMOS Technology An Introduction to Cadence Virtuoso Layout Tool and the Analog Simulation Environment Prepared By - Azhar A. Chowdhury Updated by Ming Yang

More information

Digital Integrated CircuitDesign

Digital Integrated CircuitDesign Digital Integrated CircuitDesign Lecture 8 Design Rules Adib Abrishamifar EE Department IUST Contents Design Rules CMOS Process Layers Intra-Layer Design Rules Via s and Contacts Select Layer Example Cell

More information

A Tutorial on Using the Cadence Virtuoso Editor to create a CMOS Inverter with CMOSIS5 Technology

A Tutorial on Using the Cadence Virtuoso Editor to create a CMOS Inverter with CMOSIS5 Technology A Tutorial on Using the Cadence Virtuoso Editor to create a CMOS Inverter with CMOSIS Technology Developed by Ted Obuchowicz VLSI/CAD Specialist, Dept. of Electrical and Computer Engineering Concordia

More information

CMOS Design Lab Manual

CMOS Design Lab Manual CMOS Design Lab Manual Developed By University Program Team CoreEl Technologies (I) Pvt. Ltd. 1 Objective Objective of this lab is to learn the Mentor Graphics HEP2 tools as well learn the flow of the

More information

Process technology and introduction to physical

Process technology and introduction to physical Neuromorphic Engineering II Lab 3, Spring 2014 1 Lab 3 March 10, 2014 Process technology and introduction to physical layout Today you will start to learn to use the Virtuoso layout editor XL which is

More information

Digital Fundamentals. Integrated Circuit Technologies

Digital Fundamentals. Integrated Circuit Technologies Digital Fundamentals Integrated Circuit Technologies 1 Objectives Determine the noise margin of a device from data sheet parameters Calculate the power dissipation of a device Explain how propagation delay

More information

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #2, Schematic Capture, DC Analysis, Transient Analysis (Inverter, NAND2)

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #2, Schematic Capture, DC Analysis, Transient Analysis (Inverter, NAND2) CPE/EE 427, CPE 527, VLSI Design I: Tutorial #2, Schematic Capture, DC Analysis, Transient Analysis (Inverter, NAND2) Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville

More information

DOWNLOAD PDF CADENCE WAVEFORM CALCULATOR USER GUIDE

DOWNLOAD PDF CADENCE WAVEFORM CALCULATOR USER GUIDE Chapter 1 : CSE / Cadence Tutorial The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems

More information

Single-Strip Static CMOS Layout

Single-Strip Static CMOS Layout EE244: Design Technology for Integrated Circuits and Systems Outline Lecture 6.2 Regular Module Structures CMOS Synthetic Libraries Weinberger Arrays Gate Matrix Programmable Logic Array (PLA) Storage

More information

Microelectronica. Full-Custom Design with Cadence Tutorial

Microelectronica. Full-Custom Design with Cadence Tutorial Área Científica de Electrónica Microelectronica Full-Custom Design with Cadence Tutorial AustriaMicroSystems C35B3 (HIT-Kit 3.70) Marcelino Santos Table of contends 1. Starting Cadence... 3 Starting Cadence

More information

More information can be found in the Cadence manuals Virtuoso Layout Editor User Guide and Cadence Hierarchy Editor User Guide.

More information can be found in the Cadence manuals Virtuoso Layout Editor User Guide and Cadence Hierarchy Editor User Guide. Chapter 6 Building with Layout This chapter consists of two parts. The first describes the generation of layout views and the second deals with the various tools used for verifying the layout, both physical

More information

EE5323/5324 VLSI Design I/II using Cadence

EE5323/5324 VLSI Design I/II using Cadence 1 of 18 2009-1-23 23:58 Spring 2009: EE5323/5324 VLSI Design I/II using Cadence This tutorial has been adapted from EE5323 offered in Fall 2007. Thanks to Jie Gu, Prof. Chris Kim and Satish Sivaswamy of

More information

University of California, Davis College of Engineering Department of Electrical and Computer Engineering. EEC118 EXPERIMENT No.

University of California, Davis College of Engineering Department of Electrical and Computer Engineering. EEC118 EXPERIMENT No. I. OBJECTIVE University of California, Davis College of Engineering Department of Electrical and Computer Engineering EEC118 EXPERIMENT No. 1 MAGIC TUTORIAL The objective of this experiment is to learn

More information

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science 6.374: Analysis and Design of Digital Integrated Circuits Using MAGIC Fall 2003 Issued: 9/04/00 Basic Usage

More information

ECE471/571 Energy Ecient VLSI Design

ECE471/571 Energy Ecient VLSI Design ECE471/571 Energy Ecient VLSI Design Project 2 Cadence Setup and Creation of an Inverter Due Date 11:30pm on Friday, January 30 th 2015 Introduction This project will rst walk you through the setup for

More information

MAGIC TUTORIAL. Getting Started: Background Info: RLW 10/15/98 3:12 PM

MAGIC TUTORIAL. Getting Started: Background Info: RLW 10/15/98 3:12 PM MAGIC TUTORIAL Getting Started: Login to one of the workstations located in ECEE 253 using login name iclab. There is no password so just hit [enter]. The local directory on each machine is /home/sp98/iclab.

More information

Cadence Tutorial. Introduction to Cadence 0.18um, Implementation and Simulation of an inverter. A. Moradi, A. Miled et M. Sawan

Cadence Tutorial. Introduction to Cadence 0.18um, Implementation and Simulation of an inverter. A. Moradi, A. Miled et M. Sawan Cadence Tutorial Introduction to Cadence 0.18um, Implementation and Simulation of an inverter A. Moradi, A. Miled et M. Sawan Section 1: Introduction to Cadence You will see how to create a new library

More information

Introduction to Design Architect

Introduction to Design Architect SANTA CLARA UNIVERSITY Dept. of Electrical Engineering Mentor Graphics Tutorials Introduction to Design Architect Yiching Chen Sangeetha Raman S. Krishnan I. Introduction II. This document contains a step-by-step

More information

F7000N Tip Alignment Device Guide

F7000N Tip Alignment Device Guide F7000N Tip Alignment Device Guide - Page 1 - Contents i. Tip Alignment Device Overview... 3 ii. Hardware... 4 iii. Hardware Installation... 5 iv. Setting the Device... 5 v. Device Movement... 8 vi. Tip

More information

Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology

Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology OUTLINE Introduction Mapping for Schematic and Layout Connectivity Generate Layout from Schematic Connectivity Some Useful Features

More information

Revision Notes: July2004 Generate tutorial for single transistor analysis. Based on existing schematic entry tutorial developed for ECE410

Revision Notes: July2004 Generate tutorial for single transistor analysis. Based on existing schematic entry tutorial developed for ECE410 Cadence Analog Tutorial 1: Schematic Entry and Transistor Characterization Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Revision Notes: July2004 Generate tutorial for

More information

Circuits. L3: Fabrication and Layout -1 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L3: Fabrication and Layout -1 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE60: CMOS Analog Circuits L: Fabrication and Layout - (8.8.0) B. Mazhari Dept. of EE, IIT Kanpur Suppose we have a Silicon wafer which is P-type and we wish to create a region within it which is N-type

More information

CMOS Process Flow. Layout CAD Tools

CMOS Process Flow. Layout CAD Tools CMOS Process Flow See supplementary power point file for animated CMOS process flow (see class ece410 website and/or* http://www.multimedia.vt.edu/ee5545/): This file should be viewed as a slide show It

More information

VLSI Lab Tutorial 1. Cadence Virtuoso Schematic Composer Introduction

VLSI Lab Tutorial 1. Cadence Virtuoso Schematic Composer Introduction VLSI Lab Tutorial 1 Cadence Virtuoso Schematic Composer Introduction 1.0 Introduction The purpose of the first lab tutorial is to help you become familiar with the schematic editor, Virtuoso Schematic

More information

Lab. Course Goals. Topics. What is VLSI design? What is an integrated circuit? VLSI Design Cycle. VLSI Design Automation

Lab. Course Goals. Topics. What is VLSI design? What is an integrated circuit? VLSI Design Cycle. VLSI Design Automation Course Goals Lab Understand key components in VLSI designs Become familiar with design tools (Cadence) Understand design flows Understand behavioral, structural, and physical specifications Be able to

More information

UNIT 6 CIRCUIT DESIGN

UNIT 6 CIRCUIT DESIGN UNIT 6 CIRCUIT DESIGN 1 2 HIERARCHY DESIGN CMOS LOGIC CIRCUIT DESIGN Learning outcomes FOR HIERARCHY DESIGN Student should be able to: Define hierarchy design. Explain the levels of hierarchical design.

More information

Cadence Schematic Tutorial. EEE5320/EEE4306 Fall 2015 University of Florida ECE

Cadence Schematic Tutorial. EEE5320/EEE4306 Fall 2015 University of Florida ECE Cadence Schematic Tutorial EEE5320/EEE4306 Fall 2015 University of Florida ECE 1 Remote access You may access the Linux server directly from the NEB Computer Lab using your GatorLink username and password.

More information

The Procedure for Laying out the inverter in TSMC s 0.35 micron Technogy using MOSIS SCMOS SCN4M_SUBM design rules.

The Procedure for Laying out the inverter in TSMC s 0.35 micron Technogy using MOSIS SCMOS SCN4M_SUBM design rules. Page 1 of 5 CADENCE TUTORIAL Creating Layout of an inverter: click on File->library->new a Create Library form appears, fill it as follows: in the name field enter: inverter select "Attach to existing

More information

Lay ay ut Design g R ules

Lay ay ut Design g R ules HPTER 5: Layout esign Rules Introduction ny circuit physical mask layout must conform to a set of geometric constraints or rules called as Layout esign rules before it can be manufactured using particular

More information

- create new schematic to the new project, PCB design begins with a schematic diagram, which present how components are connected

- create new schematic to the new project, PCB design begins with a schematic diagram, which present how components are connected Eagle 8.x tutorial - create a new project, Eagle designs are organized as projects - create new schematic to the new project, PCB design begins with a schematic diagram, which present how components are

More information

Digital Integrated Circuits (83-313) Lecture 2: Technology and Standard Cell Layout

Digital Integrated Circuits (83-313) Lecture 2: Technology and Standard Cell Layout Digital Integrated Circuits (83-313) Lecture 2: Technology and Standard Cell Layout Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 26 March 2017 Disclaimer: This course

More information

Composite Layout CS/EE N-type from the top. N-type Transistor. Diffusion Mask. Polysilicon Mask

Composite Layout CS/EE N-type from the top. N-type Transistor. Diffusion Mask. Polysilicon Mask Composite Layout CS/EE 6710 Introduction to Layout Inverter Layout Example Layout Design Rules Drawing the mask layers that will be used by the fabrication folks to make the devices Very different from

More information

Power IC 용 ESD 보호기술. 구용서 ( Yong-Seo Koo ) Electronic Engineering Dankook University, Korea

Power IC 용 ESD 보호기술. 구용서 ( Yong-Seo Koo ) Electronic Engineering Dankook University, Korea Power IC 용 ESD 보호기술 구용서 ( Yong-Seo Koo ) Electronic Engineering Dankook University, Korea yskoo@dankook.ac.kr 031-8005-3625 Outline Introduction Basic Concept of ESD Protection Circuit ESD Technology Issue

More information

File: 'ReportV37P-CT89533DanSuo.doc' CMPEN 411, Spring 2013, Homework Project 9 chip, 'Tiny Chip' fabricated through MOSIS program

File: 'ReportV37P-CT89533DanSuo.doc' CMPEN 411, Spring 2013, Homework Project 9 chip, 'Tiny Chip' fabricated through MOSIS program MOSIS Chip Test Report Dan Suo File: 'ReportV37P-CT89533DanSuo.doc' CMPEN 411, Spring 2013, Homework Project 9 chip, 'Tiny Chip' fabricated through MOSIS program Technology: 0.5um CMOS, ON Semiconductor

More information

ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS)

ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS) ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS) Objective Part A: To become acquainted with Spectre (or HSpice) by simulating an inverter,

More information

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group.

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Revision Notes: Jan. 2006 Updated for use with spectre simulator

More information

EE 140/240A - Full IC Design Flow Tutorial

EE 140/240A - Full IC Design Flow Tutorial Original document by Filip Maksimovic & Mike Lorek, Spring 2015, derived from earlier EE141 lab manuals Revisions for IC6 by David Burnett & Thaibao Phan, Spring 2016 Revisions made by Nandish Mehta to

More information

CADENCE SETUP. ECE4430-Analog IC Design

CADENCE SETUP. ECE4430-Analog IC Design CADENCE SETUP This short tutorial shows how to configure Cadence to use the NCSU Cadence Design Kit (CDK) with access to the ON Semiconductor C5 0.5-µm and the TSMC 0.35-µm CMOS processes libraries. In

More information

Tutorial on getting started in Cadence. Advanced Analog Circuits Spring 2015 Instructor: Prof. Harish Krishnaswamy TA: Jahnavi Sharma

Tutorial on getting started in Cadence. Advanced Analog Circuits Spring 2015 Instructor: Prof. Harish Krishnaswamy TA: Jahnavi Sharma Tutorial on getting started in Cadence Advanced Analog Circuits Spring 2015 Instructor: Prof. Harish Krishnaswamy TA: Jahnavi Sharma Getting Started Start Cadence from the terminal by using the command

More information

EXPERIMENT 1 INTRODUCTION TO MEMS Pro v5.1: DESIGNING a PIEZO- RESISTIVE PRESSURE SENSOR

EXPERIMENT 1 INTRODUCTION TO MEMS Pro v5.1: DESIGNING a PIEZO- RESISTIVE PRESSURE SENSOR EXPERIMENT 1 INTRODUCTION TO MEMS Pro v5.1: DESIGNING a PIEZO- RESISTIVE PRESSURE SENSOR 1. OBJECTIVE: 1.1 To learn and get familiar with the MEMS Pro environment and tools 1.2 To learn the basis of process

More information

Guide to the CSE 577 Lab and Cad tools

Guide to the CSE 577 Lab and Cad tools Guide to the CSE 577 Lab and Cad tools 1. Introduction The objective of this tutorial is to give you an overview to (1) setup the Cadence and Synopsys hspice tools for your account in IST 218 Lab, (2)

More information

EE434 ASIC & Digital Systems. From Layout to SPICE Simulation (Virtuoso, Calibre, HSpice) Spring 2017 Dae Hyun Kim

EE434 ASIC & Digital Systems. From Layout to SPICE Simulation (Virtuoso, Calibre, HSpice) Spring 2017 Dae Hyun Kim EE434 ASIC & Digital Systems From Layout to SPICE Simulation (Virtuoso, Calibre, HSpice) Spring 2017 Dae Hyun Kim daehyun@eecs.wsu.edu 1 Preparation for Lab2 Download the following file into your working

More information

Digital VLSI Design I

Digital VLSI Design I igital VLSI esign I MITRM XMITIO Problems Points. 4. 0. Total 6 Was the exam fair? yes no Problem 4 points Mark your yes, no, or not applicable answers for all the given choices!.. onsidering unit size

More information

Mentor Graphics VLSI CAD Tutorials

Mentor Graphics VLSI CAD Tutorials VLSI Design Flow Using Mentor-Graphics Tools Mentor Graphics VLSI CAD Tutorials School of Engineering Santa Clara University Santa Clara, CA 95053 At the Design Center, School of Engineering, of Santa

More information

6. Latches and Memories

6. Latches and Memories 6 Latches and Memories This chapter . RS Latch The RS Latch, also called Set-Reset Flip Flop (SR FF), transforms a pulse into a continuous state. The RS latch can be made up of two interconnected

More information

Introduction to ICs and Transistor Fundamentals

Introduction to ICs and Transistor Fundamentals Introduction to ICs and Transistor Fundamentals A Brief History 1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instruments 2003 Intel Pentium 4 mprocessor (55

More information

EE 434 Lecture 30. Logic Design

EE 434 Lecture 30. Logic Design EE 434 Lecture 30 Logic Design Review from last time: Hierarchical nalog Design Domains: Top Behavioral: Structural: Physical Bottom Up Design Top Down Design Bottom Review from last time: Hierarchical

More information

The HOME Tab: Cut Copy Vertical Alignments

The HOME Tab: Cut Copy Vertical Alignments The HOME Tab: Cut Copy Vertical Alignments Text Direction Wrap Text Paste Format Painter Borders Cell Color Text Color Horizontal Alignments Merge and Center Highlighting a cell, a column, a row, or the

More information

IMPLEMENTATION OF LOW POWER AREA EFFICIENT ALU WITH LOW POWER FULL ADDER USING MICROWIND DSCH3

IMPLEMENTATION OF LOW POWER AREA EFFICIENT ALU WITH LOW POWER FULL ADDER USING MICROWIND DSCH3 IMPLEMENTATION OF LOW POWER AREA EFFICIENT ALU WITH LOW POWER FULL ADDER USING MICROWIND DSCH3 Ritafaria D 1, Thallapalli Saibaba 2 Assistant Professor, CJITS, Janagoan, T.S, India Abstract In this paper

More information

Professor Muller Fall 2016 Sameet Ramakrishnan Eric Chang Adapted from prior EE140 and EE141 labs. EE 140/240A Lab 0 Full IC Design Flow

Professor Muller Fall 2016 Sameet Ramakrishnan Eric Chang Adapted from prior EE140 and EE141 labs. EE 140/240A Lab 0 Full IC Design Flow Professor Muller Fall 2016 Sameet Ramakrishnan Eric Chang Adapted from prior EE140 and EE141 labs EE 140/240A Lab 0 Full IC Design Flow In this lab, you will walk through the full process an analog designer

More information

Summer STEM Academy. VCarve Name Sign Instructions

Summer STEM Academy. VCarve Name Sign Instructions Summer STEM Academy VCarve Name Sign Instructions Follow these instructions to draw your personalized sign on the CNC router in the Woodshop / Manufacturing shop. 1. Log on to your computer and double

More information

Nokia N90 (Toshiba ET8EA3-AS) 2.0 Megapixel CMOS Image Sensor Process Review

Nokia N90 (Toshiba ET8EA3-AS) 2.0 Megapixel CMOS Image Sensor Process Review November 21, 2005 Nokia N90 (Toshiba ET8EA3-AS) 2.0 Megapixel CMOS Image Sensor Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning

More information

TABLE OF CONTENTS 1.0 PURPOSE INTRODUCTION ESD CHECKS THROUGHOUT IC DESIGN FLOW... 2

TABLE OF CONTENTS 1.0 PURPOSE INTRODUCTION ESD CHECKS THROUGHOUT IC DESIGN FLOW... 2 TABLE OF CONTENTS 1.0 PURPOSE... 1 2.0 INTRODUCTION... 1 3.0 ESD CHECKS THROUGHOUT IC DESIGN FLOW... 2 3.1 PRODUCT DEFINITION PHASE... 3 3.2 CHIP ARCHITECTURE PHASE... 4 3.3 MODULE AND FULL IC DESIGN PHASE...

More information

Verifying the Multiplexer Layout

Verifying the Multiplexer Layout 4 This chapter introduces you to interactive verification. You will perform two different tests in the Virtuoso layout editor while using Assura interactive verification products. One test uses the Design

More information

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules EE 432 VLSI Modeling and Design 2 CMOS Fabrication

More information

Magic Technology Manual #1: NMOS

Magic Technology Manual #1: NMOS Magic Technology Manual #1: NMOS John Ousterhout Computer Science Division Electrical Engineering and Computer Sciences University of California Berkeley, CA 970 (Warning: Process details often change.

More information

Click the buttons in the interactive below to learn how to navigate the Access window.

Click the buttons in the interactive below to learn how to navigate the Access window. Access 2010 Getting Started in Access Introduction Page 1 Whenever you're learning a new program, it's important to familiarize yourself with the program window and the tools within it. Working with Access

More information

CADSOFT EAGLE TUTORIAL

CADSOFT EAGLE TUTORIAL CADSOFT EAGLE TUTORIAL IEEE OPS 2013-2014 By Shubham Gandhi, Kamal Kajouke 1 Table of Contents 1. Introduction 1.1 Getting Started 1.2 Eagle Schematic Editor 1.3 The Toolbar and Command Bar 1.4 Importing

More information

Cadence Tutorial D: Using Design Variables and Parametric Analysis Document Contents Introduction Using Design Variables Apply Apply

Cadence Tutorial D: Using Design Variables and Parametric Analysis Document Contents Introduction Using Design Variables Apply Apply Cadence Tutorial D: Using Design Variables and Parametric Analysis Created for the MSU VLSI program by Casey Wallace Last Updated by: Patrick O Hara SS15 Document Contents Introduction Using Design Variables

More information

Microsoft Word 2010 Tutorial

Microsoft Word 2010 Tutorial 1 Microsoft Word 2010 Tutorial Microsoft Word 2010 is a word-processing program, designed to help you create professional-quality documents. With the finest documentformatting tools, Word helps you organize

More information

Complete Tutorial (Includes Schematic & Layout)

Complete Tutorial (Includes Schematic & Layout) Complete Tutorial (Includes Schematic & Layout) Download 1. Go to the "Download Free PCB123 Software" button or click here. 2. Enter your e-mail address and for your primary interest in the product. (Your

More information

FABRICATION TECHNOLOGIES

FABRICATION TECHNOLOGIES FABRICATION TECHNOLOGIES DSP Processor Design Approaches Full custom Standard cell** higher performance lower energy (power) lower per-part cost Gate array* FPGA* Programmable DSP Programmable general

More information

Latch-Up. Parasitic Bipolar Transistors

Latch-Up. Parasitic Bipolar Transistors Latch-Up LATCH-UP CIRCUIT Latch-up is caused by an SCR (Silicon Controlled Rectifier) circuit. Fabrication of CMOS integrated circuits with bulk silicon processing creates a parasitic SCR structure. The

More information

Working with Tables in Microsoft Word

Working with Tables in Microsoft Word Working with Tables in Microsoft Word Microsoft Word offers a number of ways to make a table. The best way depends on how you like to work, and on how simple or complex the table needs to be. 1. Click

More information

3. Implementing Logic in CMOS

3. Implementing Logic in CMOS 3. Implementing Logic in CMOS 3. Implementing Logic in CMOS Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 27 September, 27 ECE Department,

More information

EXPERIMENT 6. CMOS INVERTERS AND CMOS LOGIC CIRCUITS

EXPERIMENT 6. CMOS INVERTERS AND CMOS LOGIC CIRCUITS EXPERIMENT 6. CMOS INVERTERS AND CMOS LOGIC CIRCUITS I. Introduction I.I Objectives In this experiment, you will analyze the voltage transfer characteristics (VTC) and the dynamic response of the CMOS

More information

EE115C Digital Electronic Circuits. Tutorial 2: Hierarchical Schematic and Simulation

EE115C Digital Electronic Circuits. Tutorial 2: Hierarchical Schematic and Simulation EE115C Digital Electronic Circuits Tutorial 2: Hierarchical Schematic and Simulation The objectives are to become familiar with Virtuoso schematic editor, learn how to create the symbol view of basic primitives,

More information

Amplifier Simulation Tutorial. Design Kit: Cadence 0.18μm CMOS PDK (gpdk180) (Cadence Version 6.1.5)

Amplifier Simulation Tutorial. Design Kit: Cadence 0.18μm CMOS PDK (gpdk180) (Cadence Version 6.1.5) Amplifier Simulation Tutorial Design Kit: Cadence 0.18μm CMOS PDK (gpdk180) (Cadence Version 6.1.5) Yongsuk Choi, Marvin Onabajo This tutorial provides a quick introduction to the use of Cadence tools

More information

VBIT COURSE MATERIAL VLSI DESIGN

VBIT COURSE MATERIAL VLSI DESIGN UNIT II VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2μm CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS

More information

LTSPICE MANUAL. For Teaching Module EE4415 ZHENG HAUN QUN. December 2016

LTSPICE MANUAL. For Teaching Module EE4415 ZHENG HAUN QUN. December 2016 LTSPICE MANUAL For Teaching Module EE4415 ZHENG HAUN QUN December 2016 DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINNERING NATIONAL UNIVERSITY OF SINGAPORE Contents 1. Introduction... 2 1.1 Installation...

More information

E85: Digital Design and Computer Engineering Lab 1: Electrical Characteristics of Logic Gates

E85: Digital Design and Computer Engineering Lab 1: Electrical Characteristics of Logic Gates E85: Digital Design and Computer Engineering Lab 1: Electrical Characteristics of Logic Gates Objective The purpose of this lab is to become comfortable with logic gates as physical objects, to interpret

More information

Cadence Virtuoso Layout Connectivity Mark- Net Tutorial

Cadence Virtuoso Layout Connectivity Mark- Net Tutorial Cadence Virtuoso Layout Connectivity Mark- Net Tutorial Digital VLSI Chip Design CAD manual addendum When you re drawing layout, especially of a complex cell, it s sometimes hard to see exactly what your

More information