ΔΙΑΛΕΞΗ 5: FPGA Programming Technologies (aka: how to connect/disconnect wires/gates)

Transcription

1 ΗΜΥ 408 ΨΗΦΙΑΚΟΣ ΣΧΕΔΙΑΣΜΟΣ ΜΕ FPGAs Χειμερινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 5: FPGA Programming Technologies (aka: how to connect/disconnect wires/gates) (ack: Jurriaan Schmitz, Semiconductor Components) ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ Also based on: Roberto Bez et al., ST Microelectronics Proceedings of the IEEE, Vol. 91 no. 4, April 2003.

2 Before we start What do we need to program? What are the configuration bits? Switchbox Routing Channel CLB Routing Channel IOB Configuration Bit ΗΜΥ408 Δ05 FPGA Programming Technologies.2 Θεοχαρίδης, ΗΜΥ, 2018

3 Other bits? I/O Block configuration bits LUTs in each CLB Look up tables made from small RAM Can also be used as small memory blocks ΗΜΥ408 Δ05 FPGA Programming Technologies.3 Θεοχαρίδης, ΗΜΥ, 2018

4 So how do we connect and disconnect wires? Configure logic CLBs, LUTs, FFs Configure interconnect channel, switchbox Large number of bits 10s MB Configuration bit technology Antifuse (program once) SRAM Floating Gate (Flash) ΗΜΥ408 Δ05 FPGA Programming Technologies.4 Θεοχαρίδης, ΗΜΥ, 2018

5 MOSFET I-V Characteristics MOSFET I-V Characteristics : Linear Region - When V GS > V T, a channel is formed. I DS is dependant on the V DS voltage - When V DS = 0v, no current flows ΗΜΥ408 Δ05 FPGA Programming Technologies.5 Θεοχαρίδης, ΗΜΥ, 2018

6 Threshold Voltage MOSFET under Bias (Inversion) - as V GS gets larger, it will form an inversion layer beneath the Gate oxide by attracting the minority carriers in the substrate to the oxide-si surface. - when the surface potential of the gate reaches the bulk Fermi potential, the surface inversion will be established and an n-channel will form - this channel forms a path between the Source and Drain φ = s φ F ΗΜΥ408 Δ05 FPGA Programming Technologies.6 Θεοχαρίδης, ΗΜΥ, 2018

7 Why all these? Because it is important to understand what causes a transistor to change state What causes a transistor to STORE state? What causes a transistor to turn-off? What happens when the voltage across the gate increases above 5V(to any scale that is?) ΗΜΥ408 Δ05 FPGA Programming Technologies.7 Θεοχαρίδης, ΗΜΥ, 2018

8 Memory Non-volatile memories what are NVM method of operation EPROM, EEPROM, and Flash Reliability concerns retention endurance Scaling ΗΜΥ408 Δ05 FPGA Programming Technologies.8 Θεοχαρίδης, ΗΜΥ, 2018

9 Non-Volatile Memories A non-volatile memory is a memory that can hold its information without the need for an external voltage supply. The data can be electrically cleared and rewritten Examples: Magnetic Core Hard-disk OTP: one-time programmable (diodes/fuses) EPROM: electrically programmable ROM EEPROM: electrically erasable and programmable ROM Flash ΗΜΥ408 Δ05 FPGA Programming Technologies.9 Θεοχαρίδης, ΗΜΥ, 2018

10 IC memory classification Volatile memories Lose data when power down Non-volatile memories Keep data without power supply SRAM DRAM ROM PROM EPROM EEPROM FLASH EEPROM ΗΜΥ408 Δ05 FPGA Programming Technologies.10 Θεοχαρίδης, ΗΜΥ, 2018

11 Non-volatile memory comparison Floating gate memories ΗΜΥ408 Δ05 FPGA Programming Technologies.11 Θεοχαρίδης, ΗΜΥ, 2018

12 How does a Flash memory cell work? How does a MOS transistor work? What is a semiconductor? ΗΜΥ408 Δ05 FPGA Programming Technologies.12 Θεοχαρίδης, ΗΜΥ, 2018

13 Semiconductor essentials: properties Metallic conductor: typically 1 or 2 freely moving electrons per atom Semiconductor: typically 1 freely moving electron per atoms ΗΜΥ408 Δ05 FPGA Programming Technologies.13 Θεοχαρίδης, ΗΜΥ, 2018

14 Semiconductor essentials - resistivity ΗΜΥ408 Δ05 FPGA Programming Technologies.14 Θεοχαρίδης, ΗΜΥ, 2018

15 Semiconductors in the periodic table II III IV V VI Be B C N O Mg Al Si P S Zn Ga Ge As Se Elemental semiconductors: C, Si, Ge (all group IV) Compound semiconductors: III-V: GaAs, GaN II-VI: ZnO, ZnS, Group-III and group-v atoms are dopants ΗΜΥ408 Δ05 FPGA Programming Technologies.15 Θεοχαρίδης, ΗΜΥ, 2018

16 Semiconductor essentials: impurities Small impurities can dramatically change conductivity: slight phosphorous contamination in silicon gives many extra free electrons in the material (one per P atom!) slight aluminum contamination gives many extra holes (one per Al atom) P Al ΗΜΥ408 Δ05 FPGA Programming Technologies.16 Θεοχαρίδης, ΗΜΥ, 2018

17 (silicon lattice is of course 3D!) ΗΜΥ408 Δ05 FPGA Programming Technologies.17 Θεοχαρίδης, ΗΜΥ, 2018

18 Silicon dopants II III IV V VI Be B C N O Mg Al Si P S Boron most widely used as p-type dopant; Phosphorous and arsenic both used widely as n-type dopant Zn Ga Ge As Se In ΗΜΥ408 Δ05 FPGA Programming Technologies.18 Θεοχαρίδης, ΗΜΥ, 2018

19 Semiconductor essentials: n and p type n-type doped semiconductor e.g. silicon with phosphorus impurity electrons determine conductivity p-type doped semiconductor e.g. silicon with Al impurity holes determine conductivity p-n junction: current can only flow one way! Semiconductor diode ΗΜΥ408 Δ05 FPGA Programming Technologies.19 Θεοχαρίδης, ΗΜΥ, 2018

20 The field effect accumulation depletion inversion ΗΜΥ408 Δ05 FPGA Programming Technologies.20 Θεοχαρίδης, ΗΜΥ, 2018

21 The MOS transistor SOURCE DRAIN ΗΜΥ408 Δ05 FPGA Programming Technologies.21 Θεοχαρίδης, ΗΜΥ, 2018

22 A MOS transistor layout source gate drain source gate drain (top view) (cross section) (cross section) ΗΜΥ408 Δ05 FPGA Programming Technologies.22 Θεοχαρίδης, ΗΜΥ, 2018

23 NMOS and PMOS transistors NMOS Free electron Free hole PMOS Conducts at +V GB Conducts at -V GB NMOS + PMOS = CMOS ΗΜΥ408 Δ05 FPGA Programming Technologies.23 Θεοχαρίδης, ΗΜΥ, 2018

24 MOSFET operation (very basic) C V fb V T accumulation depletion inversion V ΗΜΥ408 Δ05 FPGA Programming Technologies.24 Θεοχαρίδης, ΗΜΥ, 2018

25 Current through the MOS transistor inversion Channel charge: Q ~ (V gs V T ) Channel current: I ~ (V gs V T ) MOS transistor - simplistic MOS transistor - real I I V gs V gs V T V T ΗΜΥ408 Δ05 FPGA Programming Technologies.25 Θεοχαρίδης, ΗΜΥ, 2018

26 So how do we connect and disconnect wires? Configure logic CLBs, LUTs, FFs Configure interconnect channel, switchbox Large number of bits 10s MB Configuration bit technology Antifuse (program once) SRAM Floating Gate (Flash) ΗΜΥ408 Δ05 FPGA Programming Technologies.26 Θεοχαρίδης, ΗΜΥ, 2018

27 Antifuse An antifuse is the opposite of a regular fuse an antifuse is normally an open circuit until you force a programming current through it (about 5 ma). In a poly diffusion antifuse the high current density causes a large power dissipation in a small area, which melts a thin insulating dielectric between polysilicon and diffusion electrodes and forms a thin (about 20 nm in diameter), permanent, and resistive silicon link. The programming process also drives dopant atoms from the poly and diffusion electrodes into the link, and the final level of doping determines the resistance value of the link. Actel calls its antifuse a programmable low-impedance circuit element (PLICE). ΗΜΥ408 Δ05 FPGA Programming Technologies.27 Θεοχαρίδης, ΗΜΥ, 2018

28 Poly-Diffusion Antifuse ΗΜΥ408 Δ05 FPGA Programming Technologies.28 Θεοχαρίδης, ΗΜΥ, 2018

29 Metal Metal Antifuse There are two advantages of a metal metal antifuse over a poly diffusion antifuse. The first is that connections to a metal metal antifuse are direct to metal the wiring layers. Connections from a poly diffusion antifuse to the wiring layers require extra space and create additional parasitic capacitance. The second advantage is that the direct connection to the low-resistance metal layers makes it easier to use larger programming currents to reduce the antifuse resistance. Average QuickLogic metal metal antifuse resistance is approximately 80 W (with a standard deviation of about 10 W ) using a programming current of 15 ma as opposed to an average antifuse resistance of 500 W (with a programming current of 5 ma) for a poly diffusion antifuse. ΗΜΥ408 Δ05 FPGA Programming Technologies.29 Θεοχαρίδης, ΗΜΥ, 2018

30 Antifuse disadvantages The size of an antifuse is limited by the resolution of the lithography equipment used to makes ICs. The Actel antifuse connects diffusion and polysilicon, and both these materials are too resistive for use as signal interconnects. To connect the antifuse to the metal layers requires contacts that take up more space than the antifuse itself, reducing the advantage of the small antifuse size. However, the antifuse is so small that it is normally the contact and metal spacing design rules that limit how closely the antifuses may be packed rather than the size of the antifuse itself. ΗΜΥ408 Δ05 FPGA Programming Technologies.30 Θεοχαρίδης, ΗΜΥ, 2018

31 Antifuse Resistance An antifuse is resistive and the addition of contacts adds parasitic capacitance. The intrinsic parasitic capacitance of an antifuse is small (approximately 1 2 ff in a 1 m m CMOS process), but to this we must add the extrinsic parasitic capacitance that includes the capacitance of the diffusion and poly electrodes (in a poly diffusion antifuse) and connecting metal wires (approximately 10 ff). These unwanted parasitic elements can add considerable RC interconnect delay if the number of antifuses connected in series is not kept to an absolute minimum. ΗΜΥ408 Δ05 FPGA Programming Technologies.31 Θεοχαρίδης, ΗΜΥ, 2018

32 Antifuse Reliability The long-term reliability of antifuses is an important issue since there is a tendency for the antifuse properties to change over time. ΗΜΥ408 Δ05 FPGA Programming Technologies.32 Θεοχαρίδης, ΗΜΥ, 2018

33 Antifuse The fabrication process and the programming current control the average resistance of a blown antifuse, but values vary. In a particular technology a programming current of 5 ma may result in an average blown antifuse resistance of about 500ohms. Increasing the programming current to 15 ma might reduce the average antifuse resistance to 100ohms Antifuses separate interconnect wires on the FPGA chip and the programmer blows an antifuse to make a permanent connection. Once an antifuse is programmed, the process cannot be reversed. This is an OTP technology (and radiation hard). An Actel 1010, for example, contains 112,000 antifuses, but we typically only need to program about 2 percent of the fuses on an Actel chip. ΗΜΥ408 Δ05 FPGA Programming Technologies.33 Θεοχαρίδης, ΗΜΥ, 2018

34 SRAM Memory SRAM Cell SRAM Configuration Mode Bit (Read/Write) Input Data Volatile 6 CMOS transistors Standard fabrication process SRAM Output ΗΜΥ408 Δ05 FPGA Programming Technologies.34 Θεοχαρίδης, ΗΜΥ, 2018

35 SRAM Technology ΗΜΥ408 Δ05 FPGA Programming Technologies.35 Θεοχαρίδης, ΗΜΥ, 2018

36 SRAM Advantages and Disadvantages Since SRAM is volatile, the FPGA must be loaded and configured at the time of chip power-up. This requires external permanent memory to provide the programming bits such as PROM, EPROM, EEPROM or magnetic disk. A major disadvantage of SRAM programming technology is its large area. It takes 4-6 transistors to implement an SRAM cell SRAM programming technology has two major advantages fast re-programmability requires only standard integrated circuit process technology. ΗΜΥ408 Δ05 FPGA Programming Technologies.36 Θεοχαρίδης, ΗΜΥ, 2018

37 Floating Gate (EPROM/EEPROM/Flash) By applying proper programming voltages, electrons jump onto floating gate Electrons on gate raise threshold voltage so transistor always off Flash switch is comprised of two transistors which share a gate ΗΜΥ408 Δ05 FPGA Programming Technologies.37 Θεοχαρίδης, ΗΜΥ, 2018

38 Flash vs. SRAM Logic and routing configured with Flash memory Can be reconfigured when ever needed Does not loose configuration when powered down Needs technology with support for floating gates Uses fine grain cells which can be configured as logic or storage ΗΜΥ408 Δ05 FPGA Programming Technologies.38 Θεοχαρίδης, ΗΜΥ, 2018

39 SRAM Versus Flash Switch & Memory Size SRAM based PLD Switch & Routing FLASH based PLD Memory Cell Memory Cell Switch & Routing ΗΜΥ408 Δ05 FPGA Programming Technologies.39 Θεοχαρίδης, ΗΜΥ, 2018

40 FLASH Floating Gate Memory ΗΜΥ408 Δ05 FPGA Programming Technologies.40 Θεοχαρίδης, ΗΜΥ, 2018

41 Floating gate animation ΗΜΥ408 Δ05 FPGA Programming Technologies.41 Θεοχαρίδης, ΗΜΥ, 2018

42 Floating gate transistor: principle V T is shifted by injecting electrons into the floating gate; It is shifted back by removing these electrons again. Floating gate Control gate ΗΜΥ408 Δ05 FPGA Programming Technologies.42 Θεοχαρίδης, ΗΜΥ, 2018

43 Channel charge in floating gate transistors unprogrammed programmed Control gate Control gate Floating gate Floating gate silicon To obtain the same channel charge, the programmed gate needs a higher control-gate voltage than the unprogrammed gate ΗΜΥ408 Δ05 FPGA Programming Technologies.43 Θεοχαρίδης, ΗΜΥ, 2018

44 Logic 0 and 1 Reading a bit means: I d 1. Apply V read on the control gate ΔV T = -Q/C pp 2. Measure drain current I d of the floating-gate transistor When cells are placed in a matrix: drain lines V read 1 I read >> 0 0 I read = 0 V gs Control gate lines ΗΜΥ408 Δ05 FPGA Programming Technologies.44 Θεοχαρίδης, ΗΜΥ, 2018

45 NOR or NAND addressing (For multi-bit memories) NOR Word = control gate; bit = drain NAND less contacts more compact ΗΜΥ408 Δ05 FPGA Programming Technologies.45 Θεοχαρίδης, ΗΜΥ, 2018

46 NAND versus NOR 10x better endurance Fast read (~100 ns) Slow write (~10 μs) Used for Code Smaller cell size Slow read (~1 μs) Faster write (~1 μs) Used for Data ΗΜΥ408 Δ05 FPGA Programming Technologies.46 Θεοχαρίδης, ΗΜΥ, 2018

47 For large memories: Array addressing ΗΜΥ408 Δ05 FPGA Programming Technologies.47 Θεοχαρίδης, ΗΜΥ, 2018

48 Larger memories: cut into blocks ΗΜΥ408 Δ05 FPGA Programming Technologies.48 Θεοχαρίδης, ΗΜΥ, 2018

49 ΗΜΥ408 Δ05 FPGA Programming Technologies.49 Θεοχαρίδης, ΗΜΥ, 2018

50 Programming and erasing the floating gate Floating gate Control gate Control gate Floating gate SiO 2 Si 3 N 4 Polysilicon ΗΜΥ408 Δ05 FPGA Programming Technologies.50 Θεοχαρίδης, ΗΜΥ, 2018

51 Program/erase of a floating gate transistor Floating gate is surrounded by insulating material. How to drive charge in and out of it? Injection/ejection mechanisms: Fowler-Nordheim tunneling (FN) Channel Hot Electron Injection (CHE) Irradiation (most common: UV, for EPROMs) ΗΜΥ408 Δ05 FPGA Programming Technologies.51 Θεοχαρίδης, ΗΜΥ, 2018

52 Program/erase mechanisms ΗΜΥ408 Δ05 FPGA Programming Technologies.52 Θεοχαρίδης, ΗΜΥ, 2018

53 Flash program and erase methods ΗΜΥ408 Δ05 FPGA Programming Technologies.53 Θεοχαρίδης, ΗΜΥ, 2018

54 CHE: Hot electron programming Field kinetic energy overcome the barrier Hot holes Hot electrons Hole substrate current Pinch-off high electric fields near drain hot carrier injection through SiO 2 Note: < 1% of the electrons will reach the floating gate power-inefficient ΗΜΥ408 Δ05 FPGA Programming Technologies.54 Θεοχαρίδης, ΗΜΥ, 2018

55 Programming: Channel Hot Electron Injection ΗΜΥ408 Δ05 FPGA Programming Technologies.55 Θεοχαρίδης, ΗΜΥ, 2018

56 CHE: properties Works only to create a positive V T shift High power consumption: ~300 µa/cell (most electrons get to the drain: lost effort) Moderate programming voltages Risky: hot carriers can damage materials May lead to fixed charge, interface traps, bulk traps Results in degradation of the cell (see later) ΗΜΥ408 Δ05 FPGA Programming Technologies.56 Θεοχαρίδης, ΗΜΥ, 2018

57 Fowler-Nordheim tunneling Uniform tunneling through entire dielectric is possible V T -shift can be positive as well as negative Can be used for program and erase Requires high voltage and high capacitances Little power needed (~10 na/cell) FN Risks of this technique: Charge trapping in oxide Stress-induced leakage current Defect-related oxide breakdown ΗΜΥ408 Δ05 FPGA Programming Technologies.57 Θεοχαρίδης, ΗΜΥ, 2018

58 Uniform or drain-side FN tunneling Non-uniform: only for erasing; less demanding for the dielectric ΗΜΥ408 Δ05 FPGA Programming Technologies.58 Θεοχαρίδης, ΗΜΥ, 2018

59 Alternative: tunnel through interpoly oxide (erasing, combined with CHE program) Less demanding for the tunnel oxide Therefore less SILC and better retention More demanding for interpoly oxide ΗΜΥ408 Δ05 FPGA Programming Technologies.59 Θεοχαρίδης, ΗΜΥ, 2018

60 NOR and NAND flash technology ΗΜΥ408 Δ05 FPGA Programming Technologies.60 Θεοχαρίδης, ΗΜΥ, 2018

61 The Floating-gate transistor (FAMOS) Source Floating gate Gate Drain D t ox G n + Substrate p t ox n +_ S Device cross-section Schematic symbol ΗΜΥ408 Δ05 FPGA Programming Technologies.61 Θεοχαρίδης, ΗΜΥ, 2018

62 Floating-Gate Transistor Programming 20 V 0 V 5 V 10 V 5 V 20 V - 5 V 0 V V 5 V S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V T. ΗΜΥ408 Δ05 FPGA Programming Technologies.62 Θεοχαρίδης, ΗΜΥ, 2018

63 A Programmable-Threshold Transistor I D 0 -state 1 -state ON DV T OFF V WL V GS ΗΜΥ408 Δ05 FPGA Programming Technologies.63 Θεοχαρίδης, ΗΜΥ, 2018

64 Floating Gate Technology - EPROM The programmable switch is a transistor that can be permanently disabled. Accomplished by injecting a charge on the floating gate (gate 2) using a high voltage between the control gate 1 and the drain of the transistor. Charge increases the threshold voltage of the transistor so that it turns off. Charge is removed by exposing the floating gate to UV light. lowers the threshold voltage of the transistor makes the transistor function normally. ΗΜΥ408 Δ05 FPGA Programming Technologies.64 Θεοχαρίδης, ΗΜΥ, 2018

65 EPROM Programming takes several microsecs/word (5-10) Erasure occurs off system Limited endurance (number of erasures) is limited to a maximum of thousand Device thresholds may vary with erasure High power dissipation during programming Extremely simple high density Fallen out of favor replaced by FLASH ΗΜΥ408 Δ05 FPGA Programming Technologies.65 Θεοχαρίδης, ΗΜΥ, 2018

66 FLOTOX EEPROM Floating gate Source Gate Drain I nm n 1 Substrate n 1 p 10 nm -10 V 10 V V GD FLOTOX transistor Fowler-Nordheim I-V characteristic Threshold is affected by initial charge; thickness of oxide and applied programming Voltage; Removing too much charge from floating gate can make transistors always ON ΗΜΥ408 Δ05 FPGA Programming Technologies.66 Θεοχαρίδης, ΗΜΥ, 2018

67 EEPROM Cell BL WL V DD Absolute threshold control is hard Unprogrammed transistor might be in depletion 2 transistor cell ΗΜΥ408 Δ05 FPGA Programming Technologies.67 Θεοχαρίδης, ΗΜΥ, 2018

68 EEPROM Advantages/Disadvantages Larger because of two cells FLOTOX intrinsically larger than FAMOS Fabrication of thin oxide is challenging and costly EEPROMS have larger erase cycles 10^5 Repeated programming causes shift in threshold voltages ΗΜΥ408 Δ05 FPGA Programming Technologies.68 Θεοχαρίδης, ΗΜΥ, 2018

69 Flash EEPROM Control gate Floating gate erasure n 1 source programming p- substrate Thin tunneling oxide n 1 drain Combines density of EPROM with versatility of EEPROM ΗΜΥ408 Δ05 FPGA Programming Technologies.69 Θεοχαρίδης, ΗΜΥ, 2018

70 Cross-sections of NVM cells Flash EPROM Courtesy Intel ΗΜΥ408 Δ05 FPGA Programming Technologies.70 Θεοχαρίδης, ΗΜΥ, 2018

71 Advanced Flash Switch Actel ProASIC3 family uses a live on power-up ISP (in system programmability) Flash switch as its programming element. Flash cells are distributed throughout the device to provide nonvolatile, reconfigurable programming to connect signal lines to the appropriate VersaTile inputs and outputs. The use of the Flash switch technology also removes the possibility of firm errors, which are increasingly common in SRAM-based FPGAs. ΗΜΥ408 Δ05 FPGA Programming Technologies.71 Θεοχαρίδης, ΗΜΥ, 2018

72 Flash Switch In the Flash switch, two transistors share the floating gate, which stores the programming information. One is the sensing transistor, which is only used for writing and verification of the floating gate voltage. The other is the switching transistor which is used to connect or separate routing nets, or to configure VersaTile logic. It is also used to erase the floating gate. ΗΜΥ408 Δ05 FPGA Programming Technologies.72 Θεοχαρίδης, ΗΜΥ, 2018

73 ΗΜΥ408 Δ05 FPGA Programming Technologies.74 Θεοχαρίδης, ΗΜΥ, 2018

74 ΗΜΥ408 Δ05 FPGA Programming Technologies.75 Θεοχαρίδης, ΗΜΥ, 2018

75 ΗΜΥ408 Δ05 FPGA Programming Technologies.76 Θεοχαρίδης, ΗΜΥ, 2018

76 ΗΜΥ408 Δ05 FPGA Programming Technologies.77 Θεοχαρίδης, ΗΜΥ, 2018

77 Basic Operations in a NOR Flash Memory Erase cell array BL 0 BL 1 12 V G 0 V WL 0 S D 12 V 0 V WL 1 open open ΗΜΥ408 Δ05 FPGA Programming Technologies.78 Θεοχαρίδης, ΗΜΥ, 2018

78 Basic Operations in a NOR Flash Memory Write 12 V G 6 V 12 V Always off BL 0 BL 1 WL 0 S D 0 V 0 V WL 1 6 V 0 V ΗΜΥ408 Δ05 FPGA Programming Technologies.79 Θεοχαρίδης, ΗΜΥ, 2018

79 Basic Operations in a NOR Flash Memory Read 5 V G 1 V 5 V BL 0 BL 1 WL 0 S D 0 V 0 V WL 1 1 V 0 V ΗΜΥ408 Δ05 FPGA Programming Technologies.80 Θεοχαρίδης, ΗΜΥ, 2018

80 NAND Flash Memory Word line(poly) Unit Cell Gate ONO Gate Oxide FG Source line (Diff. Layer) Courtesy Toshiba ΗΜΥ408 Δ05 FPGA Programming Technologies.81 Θεοχαρίδης, ΗΜΥ, 2018

81 Characteristics of State-of-the-art NVM ΗΜΥ408 Δ05 FPGA Programming Technologies.83 Θεοχαρίδης, ΗΜΥ, 2018

82 Different Technologies ΗΜΥ408 Δ05 FPGA Programming Technologies.84 Θεοχαρίδης, ΗΜΥ, 2018

83 Comparison of Technologies SRAM Antifuse Flash Speed Medium Fast Slow Power Poor Good Good Relative Size 1 1/10 1/7 Reprogram Yes No Yes Size Large Small Moderate Volatile Yes No No Security?????? ΗΜΥ408 Δ05 FPGA Programming Technologies.85 Θεοχαρίδης, ΗΜΥ, 2018

84 Some Examples Xilinx, Altera SRAM Actel Antifuse Actel, Atmel EEPROM Lattice, Actel - Flash ΗΜΥ408 Δ05 FPGA Programming Technologies.86 Θεοχαρίδης, ΗΜΥ, 2018

85 Additional Reading Architecture of Field-Programmable Gate Arrays, Proc. PROCEEDINGS OF THE IEEE. VOL 81. NO 7. JULY 1993 Chap 12: Digital Integrated Circuits Second Edition J. Rabaey et. Al. Chap 4 online text book ΗΜΥ408 Δ05 FPGA Programming Technologies.87 Θεοχαρίδης, ΗΜΥ, 2018