Texas Instruments TMX320TCI6488ZUNV Baseband Processor System on a Chip

Transcription

1 Texas Instruments TMX320TCI6488ZUNV Baseband Processor System on a Chip Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Package Analysis 3.1 Overview 3.2 Solder Balls 3.3 Printed Wiring Board 4 Process Analysis 4.1 General Device Structure 4.2 Bond Pads 4.3 Dielectrics 4.4 Metallization 4.5 Vias and Contacts 4.6 Transistors and Poly 4.7 Isolation 4.8 Wells and Substrate 5 Floor Plan Analysis 5.1 Die Floor Plan 5.2 Die Corner and Scribe Lane 5.3 Dummy Metal 5.4 Standard Logic 5.5 E-Fuse 6 High Density Six-Transistor SRAM Cell 6.1 Overview 6.2 Plan View Analysis High Density 6T SRAM 6.3 Cross-Sectional Analysis (Perpendicular to Wordline) 6.4 Cross-Sectional Analysis (Parallel to Wordline)

3 Structural Analysis 7 Low Density Six-Transistor SRAM 7.1 Overview 8 Materials Analysis 8.1 Overview 8.2 TEM-EDS Analyses of the Dielectrics 8.3 TEM-EDS Transistors, Contacts, and Poly 8.4 TEM-EDS Metallization 9 Critical Dimensions 9.1 Horizontal Dimensions 9.2 Vertical Dimensions 10 Statement of Measurement Uncertainty and Scope Variation 11 References Report Evaluation

4 Overview Overview 1.1 List of Figures 2 Device Overview Top Package View Bottom Package View Package X-Ray Die Photograph Die Markings Die Annotated with Die Cross Sections Die Corner Die Corner Die Corner Die Corner Bond Pads 3 Package Analysis Package Cross Section Die and Printed Wiring Board Solder Bumps Solder Bump Printed Wiring Board PWB Metallization Via Package Ball Edge Metal 1 Land Plating 4 Process Analysis General View of TMX320TCI6488ZUNV Die Edge Die Seal Solder Ball and Bond Pad Bond Pad Left Bond Pad Edge Passivation TEM Passivation Passivation ILD TEM ILD ILD TEM ILD TEM ILD 4 Through ILD ILD 4 and ILD ILD 2 and ILD Pre-Metal Dielectric TEM Pre-Metal Dielectric

5 Overview Minimum Width Metal TEM Metal 8 TaN Barrier Layer Minimum Pitch Metal TEM Edge of Metal 7 Line TEM Bottom Metal Minimum Pitch Metal TEM Minimum Pitch Metal TEM Metal 5 TaN Liner TEM Minimum Pitch Metal TEM Minimum Pitch Metal TEM Minimum Pitch Metal TEM Minimum Pitch metal TEM Metal 1 Liner Minimum Width Via Minimum Pitch Via 6s TEM Via Minimum Pitch Via 5s and Via 4s Minimum Pitch Via 3s and Via 2s TEM Minimum Pitch Via 2s Minimum Pitch Via 2s and Via 1s TEM Minimum Pitch Via 1s Minimum Pitch Contacts to Diffusion TEM Contacts to Diffusion TEM Contact Top TEM Contact Bottom Minimum Pitch Contacts to Poly NMOS Transistors PMOS Transistors TEM NMOS Transistor TEM 38 nm Gate Length NMOS Transistor TEM PMOS Transistor TEM Gate Oxide TEM PMOS I/O Transistor TEM Source Contact TEM PMOS I/O Transistor Sidewall Spacer TEM I/O Transistor Gate Oxide TEM Minimum Width STI in Periphery STI Over Isolation TEM STI Edge TEM Diffraction Pattern Si Channel Region SCM Peripheral Wells SRP and SIMS Peripheral P-Well SIMS Peripheral N-Well

6 Overview Floor Plan Analysis Annotated Metal 2 Die Photograph Die Corner and Scribe Lane Die Seal Scribe Lane Structures Dummy Metal Dummy Metal Dummy Metal Dummy Metal Dummy Poly and Diffusion Standard Logic at Metal Standard Logic at Poly NAND Gate E-Fuse Array at Poly E-Fuse Cell at Metal E-Fuse Cell at Poly E-Fuse 6 High Density Six-Transistor SRAM Cell T SRAM Lower Right Corner of SRAM Block at Metal Metal 3 Bitlines and Power Buses Metal 2 Wordlines Metal 1 Local Interconnects SRAM Cell at Metal SRAM at Poly SRAM Cell at Poly SRAM at Diffusion SRAM Perpendicular to Wordline TEM NMOS Transistor TEM Sidewall Spacer PMOS Pull-Up Transistors TEM PMOS Pull-Up Transistors TEM PMOS Transistor TEM SRAM Gate Oxide SRAM Cell TEM Cell Transistors TEM Minimum Width STI 7 Low Density Six-Transistor SRAM Low Density 6T SRAM at Metal Low Density 6T SRAM at Metal SRAM at Metal SRAM at Poly

7 Overview Materials Analysis TEM-EDS ILD 7 (Passivation) TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS PMD 6 and PMD TEM-EDS PMD 3 Through PMD TEM-EDS Gate Polycide TEM-EDS Gate Polysilicon TEM-EDS NMOS Sidewall Spacer Implant TEM-EDS PMOS Source/Drain Diffusion TEM-EDS Channel Region TEM-EDS Metal TEM-EDS Metal 1 Barrier Layer

8 Overview List of Tables 1 Overview Device Identification Device Summary Process Summary 2 Device Overview Package, Die, and Bond Pad Sizes 4 Process Analysis Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Peripheral Transistor Horizontal Dimensions Peripheral Transistor and Polycide Vertical Dimensions Die Thickness and Well Depths 5 Floor Plan Analysis Functional Block Sizes 6 High Density Six-Transistor SRAM Cell SRAM Dimensions 7 Low Density Six-Transistor SRAM Low Density SRAM 9 Critical Dimensions Package, Die, and Bond Pads Minimum Pitch Metals Minimum Pitch Contacts and Vias Peripheral Transistor Horizontal Dimensions High Density 6T SRAM Cell Dimensions Vertical Dimensions Dielectrics Vertical Dimensions Metals Transistor Vertical Dimensions Die and Wells Vertical Dimensions Supplementary Table Metal and Dielectric Stack Heights

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