Digital Systems. Semiconductor memories. Departamentul de Bazele Electronicii

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1 Digital Systems Semiconductor memories Departamentul de Bazele Electronicii

2 Outline ROM memories ROM memories PROM memories EPROM memories EEPROM, Flash, MLC memories Applications with ROM memories extending the memory capacity state machines signal generators RAM memories SRAM memories DRAM memories RAM write and read operations Systems with Digital Integrated Circuits Semiconductor memories 2

3 Definitions Semiconductor memory electronic circuits, fabricated on silicon, which store binary data Non-volatile memory the stored information isn t lost when the chip is not powered ROM, PROM, EPROM, EEPROM Volatile memory - the information is lost when the power supply is disconnected static RAM (SRAM), dynamic RAM (DRAM), FIFO and LIFO registers Performance characteristics: capacity: the total number of bits stored in a chip access time (delay time): which shows the speed of words processing Systems with Digital Integrated Circuits Semiconductor memories 3

4 ROM memories ROM Read Only Memory non-volatile memory that ca only be read by the user memory matrix: 2 n lines and m columns ninput address decoder decodes 2 n lines Capacity the total number of memory cells is 2 n x m. The decoder selects one of the 2 n memory lines The circuit outputs the entire information at a given memory line 2 n lines m columns Systems with Digital Integrated Circuits Semiconductor memories 4

5 ROM memories the memory cell The memory cell is placed at the intersection of a memory raw and a column Each cell being implemented with a MOS transistor with n channel All transistors on a column have the output connected implicitly to VDD pull-up logic 1 There is a load device for every column which is a n channel depletion transistor The transistor is controlled by the W k bit of line selection The transistor is driven ON and implements short-circuit to ground pull-down logical Systems with Digital Integrated Circuits Semiconductor memories 5

6 Mask programmable ROM memories MASK PROGRAMMABLE ROMs The memory cell is implemented with a transistor which is selected by the address word and must be ON or OFF, depending on the programmed information ROM programming is performed during IC fabrication using several process methods Metal contact to connect a transistor to the bit line: presence or absence of the metal contact determines 0 or 1 for the delivered data; Thin or thick gate oxide, which creates either a standard transistor or a high threshold transistor, respectively (this last one will always be off). Systems with Digital Integrated Circuits Semiconductor memories 6

7 ROM memories the memory matrix structure Another method of executing ROM memories is that instead of the cells that memorize logic 0 to be connected transistors and, for obtaining the logic 1 the transistors should miss. Presence or absence of the transistor determines 0 or 1 Example: 2x 6 bits ROM memory The production costs are bigger than in the previous cases, because all masks differ from a solution to another Memory contents: Systems with Digital Integrated Circuits Semiconductor memories 7

8 ROM memories the memory cell Memory programming is done by the producer with a programming mask the memory can only be read by the user Long production time and high costs They need thousands of chips in order to cover the costs of production which are about 20 k Euro Applications The ROM memories are wide spread today, keeping their importance after decades; Used for storing some vital information for the computer functioning, measuring devices, appliances, etc. Other applications: storing video game software, sound data in electronic music instruments, software codes for microcontrollers used in industrial applications Systems with Digital Integrated Circuits Semiconductor memories 8

9 ROM memories PROM Programmable Read Only Memory programming is done by the user by burning a fuse or antifuse programming is irreversible Fuse a material with low resistance (short circuit), which burns a high current flows through it disconnects two metal paths Antifuse a dielectric material which permanently changes its resistive state from highly resistive (interruption) to low resistance (short circuit) when a high voltage is applied connects two metal paths metal metal antifuse (dielectric) Systems with Digital Integrated Circuits Semiconductor memories 9

10 EPROM memories EPROM Erasable Programmable Read Only Memory programmable ROM memory which can be erased by the user memory element floating-gate transistor the floating gate is buried into the dielectric material between the control gate and bulk hot electron injection 5-20V voltage pulses create a strong lateral field, which causes electron acceleration and charge injection into the floating gate the floating gate becomes negatively charged, thus increasing the transistor threshold voltage Systems with Digital Integrated Circuits Semiconductor memories 10

EPROM memories Writing the EPROM memory the memory cells implicitly contain 0 I D 1 logic 0 logic write 1 voltage pulses are applied to change V th T -on ΔV th T -off Reading the stored bit the

11 EPROM memories Writing the EPROM memory the memory cells implicitly contain 0 I D 1 logic 0 logic write 1 voltage pulses are applied to change V th T -on ΔV th T -off Reading the stored bit the threshold voltage is compared to a reference level Erasing the memory the memory cells are exposed to a flux of UV radiation for approximately 20 minutes through a quartz window on the package V th1 V ref V th0 V GS the UV radiation determines the discharge of the trapped electrons in the floating gate high costs the quartz window on the memory ceramic package, the UV generator, changing the memory on the board Alternative: One-time programmable (OTP) manufactured in plastic packages cannot be erased Systems with Digital Integrated Circuits Semiconductor memories 11

12 EPROM memories EEPROM Electronically Erasable Programmable Read Only Memory programmable ROM memory which can be erased with electric methods the oxide under the floating gate is thinner than at EPROM discharging of the electrons from the floating gate is based on Fowler Nordheimtunneling, and is achieved by application of a large voltage on the control gate which induces a strong vertical field into the oxide under the gate requires two transistors per bit: select transistor and store transistor EEPROM cell access W k = 1 Writing the EEPROM the floating gate is implicitly charged (high V th ) 1 voltage impulses are applied to discharge the floating gate (low V th ) 0 Erasing the memory the floating gate is charged Systems with Digital Integrated Circuits Semiconductor memories 12

13 Flash memories Flash memory it is based on the EEPROM principle requires one transistor per memory cell Multi-level Cell (MLC) takes into consideration the analog character of the floating gate charge the threshold voltage (V th ) can be set to multiple discrete levels: 4 levels 2 bits/cell, 8 levels 3 bits/cell, etc. hierarchical organization: memory plane block word+ page cells example: 64 GB memory 4 bits / cell (16 V th levels) 64K cells / page 256 pages / block 2K blocks / plane 2 planes Systems with Digital Integrated Circuits Semiconductor memories 13

14 Applications with ROM memories Extending the memory capacity no. of lines example 4x4 memory extended to 8x4 (3 addresses) Requires two 4x4 memory blocks first block lines 0 3 second block lines 4 7 A 2 MSB is connected to CS selects between the two memory blocks A 1 and A 0 are connected to the address lines The outputs are connected together 8 linii mem 4x4 mem 4x4 4 coloane Systems with Digital Integrated Circuits Semiconductor memories 14

15 Applications with ROM memories Extending the memory capacity no. of columns example 4x4 memory extended to 4x8 (8 outputs) Requires two 4x4 memory blocks first block columns 0 3 second block columns 4 7 A 1 and A 0 are connected to the address lines the 8 outputs (4 from each block) are the extended memory outputs A 1 A 0 CS 1 CS 0 A 1 A 0 O 1 O 2 O 3 ROM 4x4 O 1 O 1 O 2 O O 4 2 O O 5 3 O 3 O 6 O 7 ROM 4x8 A 1 A 0 O 1 O 7 Systems with Digital Integrated Circuits Semiconductor memories 15

16 Applications with ROM memories Extending the memory capacity lines and columns example 4x4 memory extended to 8x8 (8 outputs) Requires four 4x4 memory blocks blocks 1and 3; 2 and 4 extends the no. of lines blocks 1+3and 2+4 extends the no. of columns mem1 4x4 mem2 4x4 8 linii mem3 4x4 mem4 4x4 8 coloane Systems with Digital Integrated Circuits Semiconductor memories 16

17 Applications with ROM memories Extending the memory capacity lines and columns example 64x4 memory extended to 256x8 DCD 2:4 Bancul 1 A 7 A 6 A 1 O 1 A 0 O 2 G O 3 CS 3 CS 2 CS 1 CS 0 O 3 ROM 256x8 A 5 A 0 A 5 A 5 A 0 O 3 ROM 64x4 Bancul 2 CS 3 CS 2 A 5 CS 1 CS 0 A 7 A 6 A 5 A 1 A 0 O 1 O 2 O 3 O 4 O 4 O 5 O 7 O 6 O 7 A 0 A 0 O 3 ROM 64x4 Systems with Digital Integrated Circuits Semiconductor memories 17

18 Applications with ROM memories Extending the memory capacity lines and columns example 64k x2 memory extended to 1Mx8 Bancul 1 16 CS 15 CS 0 CS 1 O 1 O 1 ROM 1Mx8 DCD 4:16 CS 0 A 15 A 19 A 3 A A CS 2 O A 0 A 17 A 1 A 16 A 0 CS 15 G O 15 A 15 A 0 O 1 ROM 64kx2 16 O 1 Bancul 4 CS 15 A 19 A 18 A 17 A 1 A 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7 CS 0 CS 1 A 15 O 1 O 1 O 1 O 6 O 7 A 0 ROM 64kx2 Systems with Digital Integrated Circuits Semiconductor memories 18

19 Applications with ROM memories Combinatorial logic Example 1. 2 bits adder implemented with 32x8 memory Systems with Digital Integrated Circuits Semiconductor memories 19

20 Applications with ROM memories Sequential machines Example 2. Modulo 6 counter with JK flip-flop and 32x8 memory Q 2 Q 1 Q Q 2+ Q 1+ Q X X X X X X J 2 K 2 J 1 K 1 J 0 K 0 0 X 0 X 0 X 1 X X 0 X 1 X X X X 0 X 1 X X 0 X 1 0 X 0 X X X X X 1 X X 1 1 X X 1 1 X X 1 X X X X J 2 Q 2 J 1 Q 1 J 0 Q 0 CK CK CK CK K 2 Q 2 K 1 Q 1 K 0 Q 0 Q 2 Q 1 Q 0 A O 1 4 A 3 A 2 A 1 A 0 ROM32x8 O 2 O 3 O 4 O 5 O 6 O 7 J 2 K 2 J 1 K 1 J 0 K 0 Systems with Digital Integrated Circuits Semiconductor memories 20

21 Applications with ROM memories Signal generator with counter and 32x8 memory the counter is used to generate at outputs the desired binary sequences and the counter control information is stored in the memory S = Q C Systems with Digital Integrated Circuits Semiconductor memories 21

22 Applications with ROM memories State machine with counter and 32x8 memory the counter is used to generate the states and the counter control information is stored in the memory Nr+I 0000 a 0111 I+I a a 1 M+Nr Nr M+Nr a a a a a 1 a Nr Nr+I a Nr Systems with Digital Integrated Circuits Semiconductor memories 22

23 Applications with ROM memories Signal generator with counter and 32x8 memory the counter is used as an address counter, and the desired sequences are stores in the memory Systems with Digital Integrated Circuits Semiconductor memories 23

24 RAM memories RAM Random Access Memory volatile memory random access each memory cell can be accessed independently, at any time, at the same speed, and in any location (line and column) Classification Static RAM Dynamic RAM Systems with Digital Integrated Circuits Semiconductor memories 24

25 RAM memories RAM: memory structure array of memory cells line and column address circuits column pre-charge write/read circuit sense amplifier Systems with Digital Integrated Circuits Semiconductor memories 25

26 RAM memories the SRAM cell SRAM Static RAM two stable states, 0 or 1 WL The elementary SRAM cell a latch implemented with two inverters, in a positive feedback connection BL Q Qb BL Operation principle tracking stage the latch is in a passive state, a signal is applied to the inputsq şi Qb (e.g. Q = 1 and Qb = 0 ) hold stage the input voltages are disconnected, the latch detects the Q-Qb voltage difference, which is amplified through the positive feedback mechanism, until reaching the supply voltages the logical levels are regenerated track hold Systems with Digital Integrated Circuits Semiconductor memories 26

27 The 6-transistor SRAM cell CMOS implementation of the two inverters The access transistors are implemented with NMOS transistors Word Line (WL) selects the memory line, and consequently the SRAM cell Bit Line (BL) same path for SRAM read/write Differential access (BL and BLn) speeds up the circuit and enhances the precision vs. parameter variations Low power consumption the transistors drain current only during metastable state Systems with Digital Integrated Circuits Semiconductor memories 27

28 The 12-transistor SRAM cell CMOS implementation of the three inverters and the transmission gates Inverters 1 and 3 contain 2 access transistors Separate paths for SRAM read/write Asymmetrical access one single data path BL Low power consumption the transistors drain current only during metastable state Systems with Digital Integrated Circuits Semiconductor memories 28

29 RAM memories write operation The memory cell is selected with lineand column address The write command is applied Rn/W = 1 The input signal (the data to be written) is applied to the data path Bit Line (BL) The line select signal Word Line (WL) turns the cell access transistors ON Systems with Digital Integrated Circuits Semiconductor memories 29

30 RAM memories read operation The data line is pre-charged to 1 The memory line is selected with the line address The read command is applied Rn/W = 0 The line select signal Word Line (WL) turns the cell access transistors ON The logic levels on the data lines BLis forced to the value stored in the cell Systems with Digital Integrated Circuits Semiconductor memories 30

31 The DRAM cell The memory element capacitor logical 1 the capacitor is charged logical 0 the capacitor is discharged Cell access element NMOS transistor A more compact structure (1C and 1T) in comparison to SRAM (6T or 12T) WL BL for the same capacity, the silicon area is much smaller V C C Data line Bit Line (BL) Lin eselect Word Line (WL) Systems with Digital Integrated Circuits Semiconductor memories 31

32 DRAM cell write and read operations Write: the data is applied on BL, the select signal WLputs the access transistor in the ON state and the capacitor charges to the value on BL Read: the memory line is selected with WL, the voltage level on BLis stated by the capacitor charging level WL BL V C C Between write and read the capacitor may discharge. The DRAM cell requires periodic refresh Systems with Digital Integrated Circuits Semiconductor memories 32

33 Bibliografie J. Wakerly Digital Design, Principle & Practices, Prentice Hall, 1999 Willy M. C. Sansen Analog Design Essentials, Springer, 2006 RabaeyJ.M., ChandrakasanA., NikolicB. Digital Integrated Circuits. A design perspective. Prentice Hall, Weste N.H.E, Harris D. CMOS VLSI Design. A Circuits and Systems Perspective. Pearson Addison Wesley, H. Kaeslin, Digital Integrated Circuit Design From VLSI Architecture to CMOS Fabrication, Cambridge University Press, Ercegovac, M., Lang T., Moreno J. Introduction to Digital Systems. John Wiley &Sons Inc, New-York, 1999 SorinHintea, MihaelaCirlugea, LeliaFestila. CircuiteIntegrate Digitale. EdituraUT Press, Cluj-Napoca, 2005 SorinHintea. Tehnicide proiectarea circuitelordigitalevlsi. Casa Cartiide Stiinta. Cluj- Napoca, 1998 Systems with Digital Integrated Circuits Semiconductor memories 33

Hardware Design with VHDL PLDs I ECE 443. FPGAs can be configured at least once, many are reprogrammable.

Hardware Design with VHDL PLDs I ECE 443. FPGAs can be configured at least once, many are reprogrammable. PLDs, ASICs and FPGAs FPGA definition: Digital integrated circuit that contains configurable blocks of logic and configurable interconnects between these blocks. Key points: Manufacturer does NOT determine