III. Flags of the Processor Staus Register

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1 III. Flags of the Processor Staus Register

2 INHALT 1. Meaning 2. Application 2.1 Shifts 2.2 Branches 2.3 Addition and Subtraction 2.4 Comparisons in magnitude

3 1. Meaning

4 processor status register Overflow Bit Break Bit Carry Bit Zero Bit ( Z=1, if result = 0 ) Interrupt Bit (see later) Decimal Mode Bit Negativ Bit ( N=1, if MSB = 1 ) For the blue marked flags exist Branch commands.

5 It is not useful, that all flags can be manipulated : C, D and I can be both, erased and set. V is only allowed to cancel. N, B und Z will be affected only by the internal steps of the program. When looking to the explanation of a certain command, you will also find the information, which flags will be affected by this assembler command. If I=1, no further interrupt is allowed. (see also PIAT)

6 2. Application

7 Wo werden Flags wichtig? C in Addition and Subtraktion, but also with Shift-commands oder comparisons in magnitude. N for determination of the sign. N and V using the BIT-command N, C, Z and V for Branches I of course for the administration of several origins of interrupts.

8 2.1 Shift-Commands left-shift ASL given : arithmetic shift left 0 result : ROL given : roll left result :

9 right - Shift LSR given : logical shift right 0 result : ROR given : roll right result :

10 2.2 Branch Commands example :.org $4000 (loop) ldx #4 lda A sta Ergebnis loop: asl A rol A+1 lda Ergebnis clc adc A sta Ergebnis lda Ergebnis+1 adc A+1 sta Ergebnis+1 dex bne Loop rts A:.byte $A7 $00 Ergebnis:.word $0000 ; set loop index (LI) ; MSB(A) C ; C LSB(A+1) ; no clc, as C is added to A+1 ; LI decrem., X=0 Z=1 ; Z=0 jump to loop, else continue with rts ; input or initialization ; of variables

11 List of Branch-Commands BCC : Branch, if C = 0 BCS : Branch, if C = 1 BNE : Branch, if Z = 0 BEQ : Branch, if Z = 1 BVC : Branch, if V = 0 BVS : Branch, if V = 1 BPL : Branch, if N = 0 BMI : Branch, if N = 1

12 Particularities of the Branch-Commands : Number of cycles depend on whether the condition is met : 2 cycles, if it is not met, program counter is incremented by 1. 3 cycles, if branching will take place ; then program counter will be new calculated (How? see below) even 4 cycles if exceeding or falling below page One branch-command consists of 2 bytes 1. byte : Code for comand, e.g. BNE 2. Byte : Difference Δ between current address to branch address

13 Branch-Commands in a program $ $0003 $400A $F5 = -$0B $400D - $000B -$4002

14 Current address means after incrementing the program counter, i.e. address below the branchcommand If Δ > 0 : jump forward If Δ < 0 : jump backward -128 < Δ < 127, because only one byte is reserved. Consequence : Jumping forward must not exceed 127 and jumping backward not -128.

15 Example : $4100 start: command_1 $41E8 BNE start $41EA command_cont $4100 start: command_1 $417B BNE start $417D command_cont $ $ 41EA -$ EA Amount is larger than $80 (128) $ $ 417D -$ 7D Amount is smaller than $80 (128) Not possible possible

16 2.3 Addition und Subtraction

17 Addition Addition A + B : A Carry B Addition in one row is done in two steps : first, the two data bits are added. second, the Carry produced in the row before will be added to the resulting Sum-bit.

18 Realization in Processor The first addition is done by the left half adder A half adder has two output pins : one for the Sum-bit and the other for the Carry-bit Remark : The C-bit will be produced either by the first or by the second half adder, i.e., instead of OR also XOR can be used.

20 Half adder The Half adder could be for example constructed as :

21 Addition with C-bit: high Bytes ( A+1, B+1 ) low Bytes ( A, B ) A B Carry C = C = C-Bit will be deleted for the low byte. Addition will be performed for the low Byte. C-Bit will be set to status register with respect to the calculation of the MSB row of the low bytes. This C-flag will be used for the addition of the high bytes. Addition of the high bytes will be performed.

22 Resulting Part of the Program lda A clc ; delete C before adding the lower bytes adc B sta result lda A+1 ; do not change C before adding the higher bytes adc B+1 sta result+1

23 Subtraction There exist processors having a subtraction work besides the work for addition. The 65xx-family has only an addition work. Therefore the subtraction must be performed by using the method of complements, i.e., for a subtraction A-B the 2-complement of B will be added to A. If the length of B is n bytes, then the 2 8n -complement must be used. Using the 65xx processor the 1-complement von B (simple inversion of B) will be added. In order to correct the difference to the 2-complement, the C-Bit must be set for the addition of the low bytes (see below and thenext foil). To remind : 2 - complement 1 - complement 2 8 : : B : B + 1 equal

24 Subtraction A B with C-Bit : manual : A B Borg-Bit with complement : 1 compl. of B Carry C = C = 1 A B Set C-Bit, to perform addition with 2 - Komplement

25 Resulting Part of the Program lda A sec ; setting of C before subtracting the lower bytes sbc B sta result lda A+1 ; do not change C before subtracing the higher bytes sbc B+1 sta result+1

The 6502 Instruction Set

The 6502 Instruction Set Load and Store Group LDA Load Accumulator N,Z LDX Load X Register N,Z LDY Load Y Register N,Z STA Store Accumulator STX Store X Register STY Store Y Register Arithmetic Group ADC