Appendix A: The ISA of a Small 8-bit Processor

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1 Computer Architecture in VHDL 1 Appendix A: The ISA of a Small 8-bit Processor Introduction to Small8 An Instruction Set Processor (ISP) is characterized by its instruction set, address modes (means to access data), programming model, and the presence of an instruction fetch-decode-execute sequence. These items are called the Instruction Set Architecture (ISA) of the processor. We wish to define a small 8-bit ISA that may be synthesized on field programmable gate arrays (FPGAs) accessible to the student. Our definition may be synthesized on many FPGAs or even combinations of CPLDs and memory. Therefore, the ISA should be viewed as an abstract specification independent of implementation. Its effectiveness may be judged by writing a simulator program in VHDL or C and running programs using the ISA on the simulator. Programming constructs that are difficult, or impossible, to code in using the ISA may be noted and improved by making changes in the ISA itself. The testing of the quality and efficiency of the ISA is independent of the implementation of the ISA in a target device. Once the quality of the ISA is assessed, the designer can consider the implementation step. Our choice of a moderate sized FPGA has placed some constraints on the number and type of instructions and data types. These constraints have already been anticipated in the selection of the instructions. The number of logical elements in the FPGA affects the choice of instructions, the number of registers and data paths, and the complexity of control sequences. The selected FPGA is the Altera 10K20. Its logical elements consist of 16-bit look-up tables that are sufficient to produce any logical function of four 1-bit variables. A large number of the logic elements are present. The device also contains several memory structures that can serve as random-access (RAM) or read-only (ROM) memory. The basic unit that will be used in this design contains bit words. Small8 will be specified in stages to exploit the structure of the instruction set. A very basic machine will be specified first. It will have a very basic set of registers, i.e., the accumulator and the program counter. A second data register will be included to serve as a staging area for data from memory. The accumulator and temporary register are 8-bits wide while the program counter is 16-bits wide. A simple instruction set that allows data movement, some arithmetic and logical operations, and decision making will be included. A small set of address modes sufficient for simple programming tasks will also be included in the basic design. Extensions to the basic design will be specified. These include the addition of an index register to support arrays. The index register will only be 8-bits wide requiring that its design must be carefully done to increase its usefulness. A stack pointer will then be included to allow a subroutine calling mechanism. The stack pointer will also be an 8-bit register for space reasons. This will force the stack to occupy a particular part of the memory map. The choice must be seriously considered in order not to reduce the resources of other operations. To understand the trade-offs made in order that the design may be fitted in the FPGA, a simulator should be written in a suitable programming language, e.g., C or the high-level component of VHDL. The effects of the design trade-offs can be studied before the hardware commitment is made. Tests consist of writing programs using the ISA. Running the programs using the simulator to evaluate the instruction set behavior. As new instructions and registers are added, the simulator is modified and new test programs are written and run. Then the older test programs are also run to see that nothing has been broken with the addition of the new features. Once a satisfactory compromise has been reached, hardware implementation can proceed. If an impasse is reached in which certain resources or other barrier is reached in the hardware implementation phase, changes in the ISA that are dictated at that level should be tested using the simulator to determine their effects. The development process is a series of loops that may reach clear back to the beginning specification of the instruction set. The Instruction Set and Address Modes of Small8 The Small8 instruction set, shown in Figure A-1, is derived from the Basic Instruction Set. The programming model is particularly simple. It consists of two 8-bit registers A and D. In order to support reasonably long programs the program address, and thus the program counter (PC), will be 16-bits long. The PC is used to point at the bytes of the instruction. The data type that the machine will directly handle will be an 8-bit signed or unsigned integer. Any larger data types will be handled under program control. The LOAD and STORE instructions have access to the memory. They move data between the two registers, between the instruction and the registers, and between memory and the registers. The Arithmetic, Shift, and Logical instructions may only operate on data in the A and/or D registers. An important task performed by a computer is that of decision making. In fact, without this capability, a machine is arguably not a computer. The decision making function is supported by instructions that test the various flags produced by the results of the instructions in the data movement and arithmetic/logical/shift sets. This informa-

2 Computer Architecture in VHDL 2 Data Movement: LOAD STORE RR and Absolute Address Modes Arithmetic, Logic, Shift: ADC AND LSL RR Address Mode SBC OR LSR RR Address Mode CLRC XOR RR Address Mode SETC RR Address Mode Decision Making Bcc (BPL, BMI, BNE, BEQ, BCS, BCC) Absolute Address Mode Subroutine Operations (optional) CALL RETURN Absolute/RR Address Mode Figure A-1: Small8 Instruction Set tion is carried in the Carry Out, Two s Complement Overflow, Sign, and Zero flags. The instructions test the flag and change the program counter to a new value if the test is true else program execution continues with the next instruction. A subroutine calling facility may be optionally included. It will need a place to store a return address. This may be a 16-bit register in the CPU which will allow only one level of subroutine nesting or a stack supported by a stack pointer register if more levels of nesting are needed. An address mode is a sequence of steps performed in an instruction that brings the data from its source to the operation element in the machine. Three address modes are supported in Small8. The Register-Register (RR) address mode assumes that the data operands are in the appropriate data registers (A and/or D) and any result will be returned to A, as the accumulator. The Immediate address mode (I) assumes that data is embedded in the instruction. In the Small8 machine, the data will be located in the second byte of the instruction. Only the Load instruction will be equipped with the immediate address mode. The Absolute Address mode (Abs) allows the instruction to point at data. This is one of the more flexible address modes. Since addresses in our machine are 16-bits long, the pointer in the instruction using the absolute address mode must also be 2 bytes long. A short version of this form may be used that requires only 1 byte in the instruction. The address space for the short version must be only 256 bytes long. This space may be located starting at location 0 in the memory map, or with the help of additional hardware it may be place anywhere in memory. We will define an indexed address mode (X) at this time. The address in memory is specified by the sum of the contents of an index register and a pointer embedded in the instruction. This address mode allows for arrays, among other data structures. If we desire our machine to have a stack, then stack addressing is related to indexed addressing without the inclusion of the pointer in the instruction. The stack pointer register (SP) contains the entire address into memory. Multi-byte data is stored in the memory of Small8 in little-endian order. The least significant byte (LSB) of the data is stored at an address below the most significant byte (MSB). This structure is illustrated in the left-hand part of Figure A-9. The Small8 Memory Map and Programming Model The memory map and programming model are shown in Figure A-2. While the address space defined by the PC is 2 16 bytes, the actual area implemented within the Embedded Array Blocks (EABs) of our FPGA will only be 512 bytes. External memory may be attached to fill out the address space. The machine will be forced to fetch its first instruction from address zero in response to its reset input. It is the programmer s responsibility to place the first instruction of the program at location zero in the memory. Two bytes of I/O will be defined for our machine. The memory-mapped output port at 0xFFFE will be attached to the 7-segment FLEX display digits. No hardware decoding will be used. One push button switch (FLEX_PB1) will be used as a reset signal to the processor. The other one (FLEX_PB2) will be attached to the input port bit 1 at location 0xFFFE. The keyboard clock and data inputs will be connected directly to the input port at location 0xFFFE, bits 7 and 0, respectively. No keyboard-reading state machine will be used. This task will be handled in Small8 software. The 8-bit FLEX_SWITCH will be connected to an input port at 0xFFFF. There is no physical or logical difference between the program and data spaces shown in the memory map in Figure A-2. In keeping with our small design, the two data registers (A and D in Figure A-2) are 8-bits wide. The program counter is 16-bits wide, but will be manipulated in 8-bit pieces since we will use an 8-bit ALU for all arithmetic operations. The status flags will occupy a 4-bit wide register. Their primary purpose is to serve as inputs to the con-

3 Computer Architecture in VHDL 3 0xFFFF 0xFFFE I/O 7 0 Accumulator A Data D 2 16 Program Counter PCH PCL 0x0200 Data 0x0100 Program 0x0000 Return Address Register Status Reg. C V Z S 15 0 RA or SP (optional) 15 0 Reset 8 bits Index X (16 or 8-bit, optional) Register Figure A-2: Memory Map and Programming Model for the Small8 Computer troller generating the behavior of Small8. If one desires to extend Small8 to have indexed addressing, subroutines with or without a stack, we have defined two optional registers to support the extensions. Notice that the SP and X registers may be either 16- or 8-bits wide. Machine Instruction Formats and Instruction Details The instruction formats and address modes are shown in Figure A-3. Three machine instruction formats are Arithmetic, Logic, Shift, and Return Instructions use the RR address mode which can be supported with the short format. They combine data in D with data in A. The result is returned to A Load Immediate uses the intermediate form since only a single byte of data is needed. Load, Store, Bcc, Call use the absolute address mode which is supported by the long format. The MSB and LSB of the address are in the second and third bytes of the instruction. 7 0 opcode opcode data opcode addr_low addr_high Figure A-3: Machine Instruction Format for the Small8 Computer ( little-endian order) used. The short form is appropriate for the Arithmetic/Shift/Logic instructions since they will only use the RR address mode. The arithmetic and logic instructions perform their operation on the A and D registers as shown in Register Transfer Language (RTL) form: A A.op. D The shift instructions cause the data in A to be shifted one bit to the left or right as appropriate. Set and Clear Carry operate directly on the C-bit in the Status Register. We can take advantage of the relationship between the ALU s function select input and the instruction types that belong to the Load and Arithmetic/Logic/Shift group. If the machine code format of the instruction s opcode is organized as shown in Figure A-5, we can use certain bit-fields in the opcode to directly drive the ALU s function select inputs at particularly points in the instruction. Load and Store move data between registers A and D, and between main memory and D. The RR form of LOAD and STORE perform the transfer operations A <- D and D <- A, respectively. Note that STORE is redundant with this address mode and may be omitted. The immediate address mode is implemented only for the LOAD instruction. Immediate data may be loaded

4 Computer Architecture in VHDL 4 LDAD: LDDA: only into the D register. The Sign and Zero flags should be set for all LOAD operations. Load: A D EA low mem[pc] EA high mem[pc] EA 256*EA high + EA low D mem[ea] Load: D A D mem[pc] Store: EA low mem[pc] EA high mem[pc] EA 256*EA high + EA low mem[ea] D Figure A-4: RTL for Load, Store, and Bcc Instructions with Absolute Addressing The long form of machine instruction is appropriate for many members of the instruction set. Each instruction using the absolute address mode needs a 16-bit address to complete its work. The high and low bytes must be fetched individually over the 8-bit data bus and assembled into a 16-bit number that will then be used as an address memory. Therefore, in our simple machine, we will give Load, Store, and the Branch instructions the ability to reference any location in memory by using the absolute address mode. If memory is considered to be a one-dimensional array of characters or bytes, then the following RTL describes the operations of these instructions. Notice the little-endian ordering of the addresses that follow the opcode of the instruction as shown in lines two and four of each of the examples in Figure A-4. If the programmer wishes to study the implementation of a subroutine mechanism in this ISA, then a single Return Address Register may be added to allow one level of subroutine nesting. The CALL and RETURN instructions transfer the PC contents to and from the Return Address Register in the course of their execution. A stack, while allowing much deeper nesting, is a more complex undertaking. The subroutine Return Address Register shown is converted into a Stack Pointer which is used as a pointer into a stack in the memory array. Instructions must be added to initialize the Stack Pointer. Once the stack mechanism is added, the designer usually supplies PUSH and POP instructions to allow the programmer to store data on the stack. While loops may be implemented using a combination of the SUB and Bcc instructions, one important use of loops is unavailable in the basic machine without an index register to point at the elements of an array. Multibyte numbers and strings exploit the features of an array. An index register, X, may be implemented. It can be built as an 8- or 16-bit register. This choice greatly influences how the register is used to assist addressing in the indexed-with-offset address mode, i.e., the locations of the index and the offset are affected by the length of the bit-fields that contain them. All combinations of 8- and 16-bit index registers and offset address fields in the instruction have been used by various CPU designers. The 8-bit opcode is sufficient to encode a large number of operation/address mode/register pointer combinations. Some organization of the bit-fields in the opcode can make the implementation of the underlying machine simpler. A possible organization is given in Figure A-5. As indicated in the opcode codings, there is plenty of room left to tell the underlying machine the desired instruction and operation. For three operand operations like addition, etc., the accumulator mode is followed with A being the implicit source of one operand and destination of the result. The operand register field is needed only to specify the other operand register. The LOAD instruction in RR form can share this coding. The address mode bit-field tells the underlying machine to fetch more information and how to use it for codes 1, 2, and 3. This simple machine will suffice for a thorough study of the operation of an Instruction Set Processor. Additions to its instruction set and address modes can be continued until the complexity of the current main-line 8-bit pro- Bcc: EA low mem[pc] EA high mem[pc] EA 256*EA high + EA low if (CC = True) then PC EA else end if

5 Computer Architecture in VHDL 5 Branch, Call, and Return address operand operation mode register address operation mode condition Figure A-5: Machine Opcode Format for the Small8 Computer Sample address mode coding: 0 - Register/Register 1 - Immediate 2 - Absolute 3 - Indexed with offset (optional) Sample operand register coding: 0 - A 1 - D 2 - X (optional) 3 - SP (optional) cessors are reached, e.g., the MC68HC11. Simulation Suggestions A small hint may be appropriate for handling the conversion between the unsigned char data being fetched from memory and the creation of an effective address. Consider the C program segment below. The variables used in unsigned char memory[0xffff]; unsigned char A, D; unsigned char tmp1, tmp2; unsigned pc; unsigned eff_addr; Figure A-6: A Simulation Hint ( little-endian ) tmp1 = memory[pc]; pc = pc + 1; tmp2 = memory[pc]; pc = pc + 1; eff_addr = (256 * tmp2) + tmp1; D = memory[(int)eff_addr]; this implementation of the load instruction are declared as unsigned. This makes the arithmetic operations performed in the simulation program identical to those performed in the actual hardware. In order to obscure the Endianess of the underlying host computer on which the simulator is running, we use an arithmetic operation to calculate the effective address. Unfortunately, this obscures the actual operation of our ISA that we are trying to show. Therefore, this example is simpler to understand, but it does not have the clarity that we will obtain elsewhere. The cast to int is required by C when using indices in arrays. Note in the C program segment on the right, the first 5 lines implement the immediate_address_mode function similar to the address mode function referred to in Figure A-4. The sixth line above is the execute function for the LOAD instruction.

6 Computer Architecture in VHDL 6 Figure A-7: The Instruction Set of Small8 Address Mode Instruction RR Imm Abs X Flags Data Movement LDA -- (A)* 84* 88* 8C -, -, z, s Load Accumulator (A) LDA 81 (D)* , -, z, s LDA 82 (X) , -, z, s LDA 83 (SP) , -, z, s STR -- (A)* -- F6* F7 -, -, -, - Store Accumulator (A) STR F1 (D)* , -, -, - STR F2 (X) , -, -, - STR F3 (SP) , -, -, - Arithmetic/Logic ADC 01* C c, v, z, s Add w/carry A SBC 11* C c, v, z, s Subtract w/carry from (A) CMP 91* C c, v, z, s Compare to (A) AND 21* C -, -, z, s AND to (A) OR 31* C -, -, z, s OR to (A) XOR 41* C -, -, z, s XOR to (A) Shift SLRA 50 c, v, z, s Shift (A) left arithmetic SLRL 51* -, -, z, s Shift (A) left logical SRRA 60 c, v, z, s Shift (A) right arithmetic SRRL 61* -, -, z, s Shift (A) right logical ROLRC 52* c, -, z, s Rotate (A) left through carry RORRC 62* c, -, z, s Rotate (A)right through carry Branching BCC B0* B8 -, -, -, - Branch on Carry Clear BCS B1* B9 -, -, -, - Branch on Carry Set BEQ B2* BA -, -, -, - Branch on Zero Set BMI B3* BB -, -, -, - Branch on Sign Set BNE B4* BC -, -, -, - Branch on Zero Clear BPL B5* BD -, -, -, - Branch on Sign Clear BVC B6* BE -, -, -, - Branch on V Clear BVS B7* BF -, -, -, - Branch on V Set Subroutines CALLCC C0 C8 -, -, -, - Call on Carry Clear CALLCS C1 C9 -, -, -, - Call on Carry Set CALLEQ C2 CA -, -, -, - Call on Carry Clear CALLMI C3 CB -, -, -, - Call on Carry Clear CALLNE C4 CC -, -, -, - Call on Carry Clear CALLPL C5 CD -, -, -, - Call on Carry Clear CALLVC C6 CE -, -, -, - Call on Carry Clear CALLVs C7 CF -, -, -, - Call on Carry Clear RETCC D , -, -, - Return on Carry Clear RETCS D , -, -, - Return on Carry Clear RETEQ D , -, -, - Return on Carry Clear RETMI D , -, -, - Return on Carry Clear RETNE D , -, -, - Return on Carry Clear RETPL D , -, -, - Return on Carry Clear RETVC D , -, -, - Return on Carry Clear RETVs D , -, -, - Return on Carry Clear Miscellaneous SETC F8* c, -, -, - Set Carry CLRC F9* c, -, -, - Clear Carry INCA FA* -, -, z, s Increment (A) DECA FB* -, -, z, s Decrement (A) INCX FC -, -, z, s Increment (X) DECX FD -, -, z, s Decrement (X) GFO FF* -, -, -, - Terminate simulation

7 Computer Architecture in VHDL 7 Figure A-8: Address Modes and Machine Instruction Format for Small8 Address Modes Register/Register: Immediate: Absolute: Indexed_with_Offset: R1 <- R1.op. R2 R1 <- R1.op. Memory[PC] R1 <- R1.op. Memory[Memory[PC+1] + (Memory[PC]<<8)] R1 <- R1.op. Memory[(Memory[PC+1] + (Memory[PC]<<8)) + (X)] Instruction Register (Opcode) Format formany Instructions Instruction format for Data Movement and Arith/Logic Instructions operation addmode opreg Instruction Format for Branch, Call, and Return Instructions operation addmode cc Figure A-9: Memory Map and Programming Model 0xFFFF 0xFFFE I/O 7 0 Accumulator A Data D higher address lower address MSB LSB Little Endian Data Storage 0x0200 Data 0x0100 Program 0x0000 Reset 8 bits 2 16 Program Counter Return Address Register Index Register PCH PCL Status Reg. C V Z S 15 0 RA or SP (optional) 15 0 X (16 or 8-bit, optional)

8 Computer Architecture in VHDL 8 Figure A-10: Machine Instruction Formats Arithmetic, Logic, Shift, and Return Instructions use the RR address mode which can be supported with the short format. They combine data in D with data in A. The result is returned to A Load Immediate uses the intermediate form since only a single byte of data is needed. Load, Store, Bcc, Call use the absolute address mode which is supported by the long format. The MSB and LSB of the address are in the second and third bytes of the instruction. 7 0 opcode opcode data opcode addr_lsb addr_msb

instruction 1 Fri Oct 13 13:05:

instruction 1 Fri Oct 13 13:05: instruction Fri Oct :0:0. Introduction SECTION INSTRUCTION SET This section describes the aressing modes and instruction types.. Aressing Modes The CPU uses eight aressing modes for flexibility in accessing