Systems I. Datapath Design II. Topics Control flow instructions Hardware for sequential machine (SEQ)
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1 Systems I Datapath Design II Topics Control flow instructions Hardware for sequential machine (SEQ)
2 Executing Jumps jxx Dest 7 fn Dest fall thru: XX XX Not taken target: XX XX Taken Fetch Decode Read 5 bytes Increment by 5 Do nothing Determine whether to take branch based on jump condition and condition codes Do nothing Write back Do nothing Update Set to Dest if branch taken or to incremented if not branch 2
3 Stage Computation: Jumps jxx Dest Fetch Decode icode:ifun M 1 [] valc M 4 [+1] valp +5 Read instruction byte Read destination address Fall through address Write back update Bch Cond(CC,ifun) Bch? valc : valp Take branch? Update Compute both addresses Choose based on setting of condition codes and branch condition 3
4 Executing call call Dest 8 0 Dest return: XX XX target: XX XX Fetch Decode Read 5 bytes Increment by 5 Read stack pointer Decrement stack pointer by 4 Write incremented to new value of stack pointer Write back Update stack pointer Update Set to Dest 4
5 Stage Computation: call call Dest Fetch Decode Write back update icode:ifun M 1 [] valc M 4 [+1] valp +5 valb R[%esp] vale valb + 4 M 4 [vale] valp R[%esp] vale valc Read instruction byte Read destination address Compute return point Read stack pointer Decrement stack pointer Write return value on stack Update stack pointer Set to destination Use ALU to decrement stack pointer Store incremented 5
6 Executing ret ret 9 0 return: XX XX Fetch Decode Read 1 byte Read stack pointer Increment stack pointer by 4 Read return address from old stack pointer Write back Update stack pointer Update Set to return address 6
7 Stage Computation: ret ret icode:ifun M 1 [] Read instruction byte Fetch Decode Write back update vala R[%esp] valb R[%esp] vale valb + 4 valm M 4 [vala] R[%esp] vale valm Read operand stack pointer Read operand stack pointer Increment stack pointer Read return address Update stack pointer Set to return address Use ALU to increment stack pointer Read return address from memory 7
8 Computation Steps OPl ra, rb icode,ifun icode:ifun M 1 [] Read instruction byte Fetch ra,rb valc ra:rb M 1 [+1] Read register byte [Read constant word] valp valp +2 Compute next Decode vala, srca valb, srcb vala R[rA] valb R[rB] Read operand A Read operand B vale Cond code vale valb OP vala Set CC Perform ALU operation Set condition code register valm [ read/write] Write dste R[rB] vale Write back ALU result back dstm [Write back memory result] update valp Update All instructions follow same general pattern Differ in what gets computed on each step 8
9 Computation Steps call Dest icode,ifun icode:ifun M 1 [] Read instruction byte Fetch ra,rb valc valc M 4 [+1] [Read register byte] Read constant word valp valp +5 Compute next Decode vala, srca valb, srcb valb R[%esp] [Read operand A] Read operand B vale Cond code vale valb + 4 Perform ALU operation [Set condition code reg.] Write valm dste M 4 [vale] valp R[%esp] vale [ read/write] [Write back ALU result] back update dstm valc Write back memory result Update All instructions follow same general pattern Differ in what gets computed on each step 9
10 Computed Values Fetch icode ifun ra rb valc valp Decode srca srcb dste dstm vala valb Instruction code Instruction function Instr. Register A Instr. Register B Instruction constant Incremented Register ID A Register ID B Destination Register E Destination Register M Register value A Register value B vale ALU result Bch Branch flag valm Value from memory 10
11 SEQ Hardware Key Blue boxes: predesigned hardware blocks E.g., memories, ALU Gray boxes: control logic Describe in HCL White ovals: labels for signals Thick lines: 32-bit word values Thin lines: 4-8 bit values Dotted lines: 1-bit values Decode Fetch Bch CC icode ifun ra Mem. control ALU A Instruction memory new New rb read write vale ALU valc Data memory Addr ALU B valm data out Data valp vala increment ALU fun. valb A B M Register file E dste dstm srca srcb dste dstm srca srcb Write back 11
12 Summary Today Control flow instructions Hardware for sequential machine (SEQ) Next time Control logic for instruction execution Timing and clocking 12
13 Systems I Datapath Design III Topics Control logic for instruction execution Timing and clocking 13
14 Fetch Logic icode ifun ra rb valc valp Instr valid Need valc Need regids increment Split Byte 0 Align Bytes 1-5 Instruction memory Predefined Blocks : Register containing Instruction memory: Read 6 bytes ( to +5) Split: Divide instruction byte into icode and ifun Align: Get fields for ra, rb, and valc 14
15 Fetch Logic icode ifun ra rb valc valp Instr valid Need valc Need regids increment Split Byte 0 Align Bytes 1-5 Instruction memory Control Logic Instr. Valid: Is this instruction valid? Need regids: Does this instruction have a register bytes? Need valc: Does this instruction have a constant word? 15
16 Fetch Control Logic nop 0 0 halt 1 0 rrmovl ra, rb 2 0 ra rb irmovl V, rb rb V rmmovl ra, D(rB) 4 0 ra rb D mrmovl D(rB), ra 5 0 ra rb D OPl ra, rb 6 fn ra rb jxx Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushl ra A 0 ra 8 popl ra B 0 ra 8 bool need_regids = icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, IIRMOVL, IRMMOVL, IMRMOVL }; bool instr_valid = icode in { INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL }; 16
17 Decode Logic Register File Read ports A, B Write ports E, M Addresses are register IDs or 8 (no access) vala valb A B M Register file E dste dstm srca srcb dste dstm srca srcb valm vale Control Logic srca, srcb: read port addresses icode ra rb dsta, dstb: write port addresses 17
18 A Source Decode Decode Decode Decode Decode Decode OPl ra, rb vala R[rA] rmmovl ra, D(rB) vala R[rA] popl ra vala R[%esp] jxx Dest call Dest ret vala R[%esp] Read operand A Read operand A Read stack pointer No operand No operand Read stack pointer int srca = [ icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL } : ra; icode in { IPOPL, IRET } : RESP; 1 : RNONE; # Don't need register ]; 18
19 E Destination Write-back Write-back Write-back Write-back Write-back Write-back OPl ra, rb R[rB] vale rmmovl ra, D(rB) popl ra R[%esp] vale jxx Dest call Dest R[%esp] vale ret R[%esp] vale Write back result None Update stack pointer None Update stack pointer Update stack pointer int dste = [ icode in { IRRMOVL, IIRMOVL, IOPL} : rb; icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP; 1 : RNONE; # Don't need register ]; 19
20 Logic Units ALU Implements 4 required functions Generates condition code values CC Register with 3 condition code bits bcond Computes branch flag Control Logic Set CC: Should condition code register be loaded? ALU A: Input A to ALU ALU B: Input B to ALU ALU fun: What function should ALU compute? Bch bcond CC Set CC ALU A vale ALU ALU B icode ifun valc vala valb ALU fun. 20
21 ALU A Input OPl ra, rb vale valb OP vala rmmovl ra, D(rB) vale valb + valc popl ra vale valb + 4 jxx Dest call Dest vale valb + 4 Perform ALU operation Compute effective address Increment stack pointer No operation Decrement stack pointer ret vale valb + 4 Increment stack pointer int alua = [ icode in { IRRMOVL, IOPL } : vala; icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valc; icode in { ICALL, IPUSHL } : -4; icode in { IRET, IPOPL } : 4; # Other instructions don't need ALU ]; 21
22 ALU Operation OPl ra, rb vale valb OP vala Perform ALU operation rmmovl ra, D(rB) vale valb + valc popl ra vale valb + 4 jxx Dest call Dest vale valb + 4 Compute effective address Increment stack pointer No operation Decrement stack pointer ret vale valb + 4 Increment stack pointer int alufun = [ icode == IOPL : ifun; 1 : ALUADD; ]; 22
23 Logic valm Reads or writes memory word Control Logic Mem. read: should word be read? Mem. write: should word be written? Mem. addr.: Select address icode Mem. read Mem. write read write Data memory Mem addr vale data out Mem data data in vala valp Mem. data.: Select data 23
24 Address OPl ra, rb No operation rmmovl ra, D(rB) M 4 [vale] vala popl ra valm M 4 [vala] jxx Dest call Dest M 4 [vale] valp ret valm M 4 [vala] Write value to memory Read from stack No operation Write return value on stack Read return address int mem_addr = [ icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : vale; icode in { IPOPL, IRET } : vala; # Other instructions don't need address ]; 24
25 Read OPl ra, rb rmmovl ra, D(rB) M 4 [vale] vala popl ra valm M 4 [vala] jxx Dest call Dest M 4 [vale] valp ret valm M 4 [vala] No operation Write value to memory Read from stack No operation Write return value on stack Read return address bool mem_read = icode in { IMRMOVL, IPOPL, IRET }; 25
26 Update Logic New Select next value of New icode Bch valc valm valp 26
27 Update update OPl ra, rb valp Update rmmovl ra, D(rB) update valp Update popl ra update valp Update jxx Dest update Bch? valc : valp Update call Dest update valc Set to destination ret update valm Set to return address int new_pc = [ icode == ICALL : valc; icode == IJXX && Bch : valc; icode == IRET : valm; 1 : valp; ]; 27
28 SEQ Operation State register Combinational Logic CC Read Read Ports Data memory Register file Write Write Ports Cond. Code register Data memory Register file All updated as clock rises Combinational Logic ALU Control logic 0x00c reads Instruction memory Register file Data memory 28
29 SEQ Operation #2 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 100 Read Read Ports Data memory Register file %ebx = 0x100 Write Write Ports state set according to second irmovl instruction combinational logic starting to react to state changes 0x00c 29
30 SEQ Operation #3 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC Read Read Ports Data memory Register file %ebx = 0x100 Write Write Ports state set according to second irmovl instruction combinational logic generates results for addl instruction 0x00c 0x00e 30
31 SEQ Operation #4 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 000 Read Read Ports Data memory Register file %ebx = 0x300 Write Write Ports state set according to addl instruction combinational logic starting to react to state changes 0x00e 31
32 SEQ Operation #5 Clock Cycle 1: Cycle 2: Cycle 3: Cycle 4: Cycle 1 Cycle 2 Cycle 3 Cycle 4 0x000: irmovl $0x100,%ebx # %ebx <-- 0x100 0x006: irmovl $0x200,%edx # %edx <-- 0x200 0x00c: addl %edx,%ebx # %ebx <-- 0x300 CC < x00e: je dest # Not taken Combinational Logic CC 000 Read Write Data memory Read Write Ports Ports Register file %ebx = 0x300 state set according to addl instruction combinational logic generates results for je instruction 0x00e 0x013 32
33 SEQ Summary Implementation Express every instruction as series of simple steps Follow same general flow for each instruction type Assemble registers, memories, predesigned combinational blocks Connect with control logic Limitations Too slow to be practical In one cycle, must propagate through instruction memory, register file, ALU, and data memory Would need to run clock very slowly Hardware units only active for fraction of clock cycle 33
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