CS 3330: SEQ part September 2016

Transcription

1 1 CS 3330: SEQ part 2 15 September 2016

2 Recall: Timing 2 compute new values between rising edges compute compute compute compute clock signal registers, memories change at rising edges next value register current value address next value (if writing) Data current value (if reading)

3 Recall: Computing components A B A OP B a b c d MUX select output MUXes switches, select one of several inputs as output based on select signal. does the primary math for instructions 3

4 Recall: Stages 4 fetch read instruction memory, split instruction decode read execute arithmetic (including of addresses) memory read or write data memory write back write to update compute next value of

5 SEQ: Instruction Fetch 5 read instruction memory at split into seperate wires: icode:ifun opcode, register numbers valc call target or mov displacement compute next instruction address: valp (instr )

6 SEQ: Instruction Decode 6 read registers vala, valb register values

7 SEQ:, 7 always read,? Problems: push pop call ret extra signals:, computed input register MUX controlled by icode

8 SEQ: Possible registers to read 8 instruction halt, nop, jcc, irmovq none none cmovcc, rrmovq none mrmovq none rmmovq, OPq call, ret none? pushq, popq (none) F icode MUX logic

9 SEQ: Possible registers to read 8 instruction halt, nop, jcc, irmovq none none cmovcc, rrmovq none mrmovq none rmmovq, OPq call, ret none? pushq, popq (none) F icode MUX logic

10 SEQ: Execute 9 perform operation (add, sub, xor, neq) output read prior condition codes Cnd condition codes based on ifun (instruction type for jcc/cmovcc) write new condition codes

11 SEQ: operations? inputs always vala, valb (register values)? no, inputs from instruction: (Displacement ) mrmovq valb rmmovq valc no, constants: (rsp /- 8) pushq popq call ret extra signals:, computed input values MUX 10

12 SEQ: Memory 11 read or write data memory valm value read from memory (if any)

13 SEQ: Control Signals for Memory 12 read/write write enable? Addr address mostly output tricky cases: popq, ret Data value to write mostly valb tricky cases: call, push

14 SEQ: Write back write registers 13

15 14 SEQ: Control Signals for WB two write inputs two needed by popq valm (memory output), ( output) two register numbers, write disable use dummy register number F MUX

16 SEQ: Update choose value for next cycle (input to register) usually valp (following instruction) exceptions: call, jcc, ret 15

17 A Starting Circuit R[] R[] next R[] next R[] xor/and ( ZF/SF 16

18 A Starting Circuit R[] R[] next R[] next R[] xor/and ( ZF/SF 16

19 A Starting Circuit R[] R[] next R[] next R[] xor/and ( ZF/SF 16

20 Circuit: Setting MUXes 17 R[] R[] next R[] next R[] xor/and ( ZF/SF

21 Circuit: Setting MUXes 17 M[1] next R[] next R[] M[2] R[] R[8] R[] R[9] xor/and add ( Four MUXes,,, ZF/SF Exercise: what do they select when running addq %r8, %r9?

22 Circuit: Setting MUXes 17 M[1] next R[] next R[] M[2] R[] R[8] R[] R[9] xor/and add ( Four MUXes,,, ZF/SF Exercise: what do they select when running addq %r8, %r9?

23 Circuit: Setting MUXes 17 R[] R[] next R[] next R[] Four MUXes,,, ZF/SF Exercise: what do they select for rmmovq? xor/and (

24 Circuit: Setting MUXes 17 R[] R[] next R[] next R[] Four MUXes,,, ZF/SF Exercise: what do they select for rmmovq? xor/and (

25 Circuit: Incomplete (1) R[] R[] next R[] next R[] xor/and ( ZF/SF 18

26 Circuit: Incomplete (1) R[] R[] next R[] next R[] xor/and ( rrmovq, irmovq, mrmovq, rmmovq, ZF/SFjmp, call, pushq, ret How many of the above instructions can the above circuit not run? (Ignore undrawn mux selector inputs.) 18

27 Circuit: Incomplete (1) R[] R[] next R[] next R[] xor/and ( rrmovq no way to connect R[] ZF/SF to input Option 1: mux on line to next R[] Option 2: mux on input to 18

28 Circuit: Incomplete (1) R[] R[] next R[] next R[] xor/and ( rrmovq no way to connect R[] ZF/SF to input Option 1: mux on line to next R[] Option 2: mux on input to 18

29 Circuit: Incomplete (1) R[] R[] next R[] next R[] xor/and ( rrmovq no way to connect R[] ZF/SF to input Option 1: mux on line to next R[] Option 2: mux on input to 0 18

30 Circuit: Incomplete (1) R[] R[] next R[] next R[] xor/and ( irmovq originally, no way to connect ZF/SF V to input adding mux on already enough 0 18

31 Circuit: Incomplete (1) R[] R[] next R[] next R[] 0 xor/and ( pushq no way to use rsp ZF/SF 18

32 Circuit: Incomplete (1) R[] R[] next R[] next R[] 0 8 xor/and ( pushq no way to use rsp ZF/SF Step 1: add mux on, Step 2: add to mux (allow constant) 18

33 Circuit: Incomplete (1) R[] R[] next R[] next R[] call no way to connect to data ZF/SF memory 0 8 xor/and ( 18

34 Circuit: Incomplete (1) R[] R[] next R[] next R[] call no way to connect to data ZF/SF memory add mux on data memory data in (allow ) 0 8 xor/and ( 18

35 Circuit: Incomplete (1) R[] R[] next R[] next R[] 0 8 xor/and ( ZF/SF 18

36 Circuit: More complete R[] R[] next R[] next R[] 0 8 xor/and ( ZF/SF 19

37 Circuit: More complete R[] R[] next R[] next R[] xor/and ( Seven MUXes,,,, ZF/SF,, data memory in Selectors for pushq?

38 Circuit: More complete R[] R[] next R[] next R[] xor/and ( Seven MUXes,,,, ZF/SF,, data memory in Selectors for pushq?

39 Circuit: More complete R[] R[] next R[] next R[] Instructions not covered: ret, popq, ZF/SF cmovcc, jcc Missing condition codes for cmovcc, jcc. 0 8 xor/and ( 19

40 Circuit: More complete R[] R[] next R[] next R[] What s wrong with this implementation ZF/SF of popq? How could it be fixed? 0 8 xor/and add ( 19

41 Circuit: More complete R[] R[] next R[] next R[] What s wrong with this implementation ZF/SF of popq? How could it be fixed? 0 8 xor/and add ( 19

42 Circuit: More complete R[] R[] next R[] next R[] 0 8 xor/and ( What do we need to add for ret? ZF/SF 19

43 Circuit: More complete R[] R[] next R[] next R[] 0 8 xor/and ( What do we need to add for ret? ZF/SF 19

44 Circuit: More complete R[] R[] next R[] next R[] 0 8 xor/and ( ZF/SF 19

45 Circuit R[] R[] next R[] next R[] 0 8 xor/and ( ZF/SF 20

46 Stages: pushq/popq stage pushq popq fetch decode icode : ifun M 1 [] : M 1 [ 1] valp 2 vala R[] valb R[] icode : ifun M 1 [] : M 1 [ 1] valp 2 vala R[] valb R[] execute valb ( 8) valb 8 memory M 8 [] vala valm M 8 [ vala ] write back R[] R[] R[] valm update valp valp 21

47 Stages: pushq/popq stage pushq popq fetch decode icode : ifun M 1 [] : M 1 [ 1] valp 2 vala R[] valb R[] icode : ifun M 1 [] : M 1 [ 1] valp 2 vala R[] valb R[] execute valb ( 8) valb 8 memory M 8 [] vala valm M 8 [ vala ] write back R[] R[] R[] valm update valp valp 21

48 Conditional movs absolutevaluejumps: andq %rdi, %rdi jge same ; if rdi >= 0, goto same irmovq $0, %rax ; rax < 0 subq %rdi, %rax ; rax < rax (0) rdi ret same: rrmovq %rdi, %rax ret absolutevaluecmov: irmovq $0, %rax subq %rdi, %rax andq %rdi, %rdi cmovge %rdi, %rax ret ; rax < rdi ; if (rdi > 0) rax < rd 22

49 Using condition codes: cmov (always) 1 (le) SF ZF (l) SF NOT cc (from instr) 23

50 Systematic construction 24 MUX OPq ret callq pushq next len memory out from instr len

51 Summary each instruction takes one cycle divided into stages for design convenience read values from previous cycle send new values to state components control what is sent with MUXes 25