Systems I. Datapath Design II. Topics Control flow instructions Hardware for sequential machine (SEQ)

Transcription

1 Systems I Datapath Design II Topics Control flow instructions Hardware for sequential machine (SEQ)

2 Executing Jumps jxx Dest 7 fn Dest fall thru: XX XX Not taken target: XX XX Taken Read 5 bytes Increment PC by 5 Do nothing Determine whether to take branch based on jump condition and condition codes Do nothing Write back Do nothing PC Update Set PC to Dest if branch taken or to incremented PC if not branch 2

3 Stage Computation: Jumps jxx Dest icode:ifun M 1 [PC] Read instruction byte valc M 4 [PC+1] valp PC+5 Read destination address Fall through address Write back PC update Bch Cond(CC,ifun) PC Bch? valc : valp Take branch? Update PC Compute both addresses Choose based on setting of condition codes and branch condition 3

4 Executing call call Dest 8 0 Dest return: XX XX target: XX XX Read 5 bytes Increment PC by 5 Read stack pointer Decrement stack pointer by 4 Write incremented PC to new value of stack pointer Write back Update stack pointer PC Update Set PC to Dest 4

5 Stage Computation: call Write back PC update call Dest icode:ifun M 1 [PC] valc M 4 [PC+1] valp PC+5 valb R[%esp] vale valb + 4 M 4 [vale] valp R[%esp] vale PC valc Read instruction byte Read destination address Compute return point Read stack pointer Decrement stack pointer Write return value on stack Update stack pointer Set PC to destination Use ALU to decrement stack pointer Store incremented PC 5

6 Executing ret ret 9 0 return: XX XX Read 1 byte Read stack pointer Increment stack pointer by 4 Read return address from old stack pointer Write back Update stack pointer PC Update Set PC to return address 6

7 Stage Computation: ret ret icode:ifun M 1 [PC] Read instruction byte Write back PC update vala R[%esp] valb R[%esp] vale valb + 4 valm M 4 [vala] R[%esp] vale PC valm Read operand stack pointer Read operand stack pointer Increment stack pointer Read return address Update stack pointer Set PC to return address Use ALU to increment stack pointer Read return address from memory 7

8 Computation Steps Write back PC update icode,ifun ra,rb valc valp vala, srca valb, srcb vale Cond code valm dste dstm PC OPl ra, rb icode:ifun M 1 [PC] ra:rb M 1 [PC+1] valp PC+2 vala R[rA] valb R[rB] vale valb OP vala Set CC R[rB] vale PC valp Read instruction byte Read register byte [Read constant word] Compute next PC Read operand A Read operand B Perform ALU operation Set condition code register [ read/write] Write back ALU result [Write back memory result] Update PC All instructions follow same general pattern Differ in what gets computed on each step 8

9 Computation Steps call Dest icode,ifun icode:ifun M 1 [PC] Read instruction byte ra,rb valc valc M 4 [PC+1] [Read register byte] Read constant word valp valp PC+5 Compute next PC vala, srca valb, srcb valb R[%esp] [Read operand A] Read operand B vale Cond code vale valb + 4 Perform ALU operation [Set condition code reg.] Write valm dste M 4 [vale] valp R[%esp] vale [ read/write] [Write back ALU result] back PC update dstm PC PC valc Write back memory result Update PC All instructions follow same general pattern Differ in what gets computed on each step 9

10 Computed Values icode ifun ra rb valc valp srca srcb dste dstm vala valb Instruction code Instruction function Instr. Register A Instr. Register B Instruction constant Incremented PC Register ID A Register ID B Destination Register E Destination Register M Register value A Register value B vale Bch ALU result Branch flag valm Value from memory 10

11 SEQ Hardware Key Blue boxes: predesigned hardware blocks E.g., memories, ALU Gray boxes: control logic Describe in HCL White ovals: labels for signals Thick lines: 32-bit word values Thin lines: 4-8 bit values Dotted lines: 1-bit values PC Bch CC icode ifun ra Mem. control ALU A Instruction memory PC newpc New PC rb read write vale ALU valc Data memory Addr ALU B valm data out Data valp vala PC increment ALU fun. valb A B M Register file E dste dstm srca srcb dste dstm srca srcb Write back 11

12 Summary Today Control flow instructions Hardware for sequential machine (SEQ) Next time Control logic for instruction execution Timing and clocking 12