Packages and Aliases. Prof. K. J. Hintz. Department of Electrical and Computer Engineering George Mason University
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1 Packages and Aliases Prof. K. J. Hintz Department of Electrical and Computer Engineering George Mason University 1
2 Packages Method for Grouping Related Declarations Which Serve a Common Purpose Set of subprograms to operate on particular data type Set of declarations for particular model Separate interface from implementation Reusable 2
3 Packages Unclutter rest of model Allows declaration of global signals, e.g., clocks.» Not a generally good since behavior can change through means other than signals declared in entity interface 3
4 Packages Design Unit Similar to Entity Declarations and Architecture Bodies Can be put in library and made accessible to other units Access to items declared in the package is through using its Selected Name library_name.package_name.item_name Aliases can be used to allow shorter names for accessing declared items 4
5 Packages Two Components to Packages Package declaration Package body 5
6 Package Declaration Subprograms Using Header, Implementation Is Hidden information hiding Constants, Do Not Need to Be Initialized in Declaration information hiding 6
7 Package Declaration Types, Must Be Completely Specified Can have variable size arrays Signals Must Be Completely Specified 7
8 Package Declaration Syntax package identifier is { package_declarative_item } end [ package ] [ identifier ] ; 8
9 Package Declaration Example* package dp32_types is constant unit_delay : Time := 1 ns ; type bool_to_bit_table is array ( boolean ) of bit ;... *Ashenden VHDL cookbook 9
10 Package Declaration Example* function bits_to_int ( bits : in bit_vector ) return integer ; function bits_to_natural ( bits : in bit_vector ) return natural ; procedure int_to_bits ( int : in integer ; bits : out bit_vector ) ; end dp32_types ; *Ashenden VHDL cookbook 10
11 Package Body Not Necessary If Package Declaration Does Not Declare Subprograms May Contain Additional Declarations Which Are Local to the Package Body Cannot declare signals in body 11
12 Package Body Declared Subprograms Must Include the Full Declaration As Used in Package Declaration Numeric literals can be written differently if same value Simple name may be replaced by a selected name provided it refers to same item 12
13 Package Body Syntax package body identifier is { package_body_declarative_item } end [ package body ] [ identifier ] ; 13
14 Package Body Example* package body dp32_types is constant bool_to_bit : bool_to_bit_table := ( false => '0', true => '1' ) ; function resolve_bit_32 ( driver : in bit_32_array ) return bit_32 is constant float_value : bit_32 := X"0000_0000" ; variable result : bit_32 := float_value ; *Ashenden VHDL cookbook 14
15 Package Body Example* begin for i in driver'range loop result := result or driver ( i ) ; end loop ; return result ; end resolve_bit_32 ; *Ashenden VHDL cookbook 15
16 Library Clause Makes Items in a Library Available to a VHDL Model To Access Items in a Library Need to Use Their selected_name library identifier {,... } ; 16
17 Use Clause Tedious to Always Use an Item s Selected Name All Items Declared in a Package or Library Can Be Made Visible Through a Use Clause 17
18 Use Clause Can Be Used in Any Declarative Section Keyword All Imports All Identifiers 18
19 Use Clause Syntax use selected_name {,... } selected_name <= name. ( identifier character_literal operator_symbol all ) 19
20 Use Clause Example* use work.dp32_types.all ; entity dp32 is generic ( Tpd : Time := unit_delay ) ; port ( d_bus : inout bus_bit_32 bus ; a_bus : out bit_32 ; read, write, fetch : out bit ; ready, phi1, phi2, reset : in bit ) ; end dp32 ; *Ashenden VHDL cookbook 20
21 Aliases Alternative Identifier for an Item Improves Readability Allows One to Differentiate Among Identically Named Items in Different Packages Can Refer to a Single Element or Part of a Composite Data Type, e.g., alias interrupt_level is PSW(30 downto 26); 21
22 Aliases Operations on Aliases Operate on Actual Items Except for the Following Attributes x simple_name x path_name x instance_name 22
23 Aliases Cannot Declare Aliases for Labels Loop parameters Generate parameters (replicates items) 23
24 Data Alias Syntax alias identifier [ : subtype_indication ] is name ; 24
25 Data Alias Subtype_indication Allows for the Type to Be Changed If scalar original» Direction cannot change» Bounds cannot change» Unconstrained type allowed 25
26 Data Alias Subtype_indication Allows for the Type to Be Changed If array or array slice» Direction can differ» Bounds can differ» Base type must remain unchanged 26
27 Non-Data Alias Syntax alias ( identifier character_literal operator_symbol ) is name [ signature ] ; 27
28 Non-Data Alias Alias for Enumeration Type Does Not Require Definition of Aliases for Enumeration Literals of Original Alias for Physical Type Retains Units Without Redefinition 28
29 Non-Data Alias Syntax Optional Signature Only for subprograms and enumeration literals Overloading of identifiers may require means of differentiating among alternatives» return type does this Outer [ ] are required 29
30 Non-Data Alias Syntax signature <= [ [ type_mark {,... } ] [ return type_mark ] ] e.g., alias high is std.standard. 1 [ return bit ] 30
31 Resolved Signals VHDL Requires a Function to Specify the Values Which Result From Tying Multiple Outputs Together Resolved Signal Includes Resolution Function Inclusion of function indicates it is a resolved signal 31
32 Resolved Signals Resolution Function Must Be Written for an Indeterminate Number of Signals Since It Is Not Known When Declared How Many Signals Will Be Connected to It. The Value of a Signal at a Transaction Is Determined by the Resolution Function Operating on the Multiply Connected Signals. 32
33 Resolved Signal Syntax subtype_indication <= [ resolution_function_name ] type_mark [ range ( range_attribute_name simple_expression ( to downto ) simple_expression) ( discrete_range {,... } ) ] ; 33
34 Resolved Signal Example* package MVL4 is type MVL4_ulogic is ( X, 0, 1, Z ); type MVL4_ulogic_vector is array ( natural range <> ) of MVL4_ulogic ; function resolve_mvl4 ( contribution : MVL4_ulogic_vector ) return MVL4_ulogic ; *Ashenden 34
35 Resolved Signal Example* subtype MVL4_logic is resolve_mvl4 MVL4_ulogic ; end package MVL4 ; *Ashenden 35
36 Resolved Signal Example* package body MVL4 is type table is array ( MVL4_ulogic, MVL4_ulogic ) of MVL4_ulogic ; 36
37 Resolved Signal Example* constant resolution_table : table := -- X 0 1 Z ( ( X X X X ), -- X ( X 0 X 0 ), -- 0 ( X X 1 1 ), -- 1 ( X 0 1 Z ) ) ;-- Z 37
38 Resolved Signal Example* function resolve_mvl4 ( contribution : MVL4_ulogic_vector ) return MVL4_ulogic is variable result : MVL4_ulogic := Z ; 38
39 Resolved Signal Example* begin for index in contribution range loop result := resolution_table ( result, contribution ( index ) ) ; end loop ; return result ; end function resolve_mvl4 ; end package body MVL4 ; 39
40 End of Lecture 40
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