Hardware Modeling. VHDL Basics. ECS Group, TU Wien
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1 Hardware Modeling VHDL Basics ECS Group, TU Wien
2 VHDL Basics 2 Parts of a Design Unit Entity Architecture Configuration Package Package Package Body Library
3 How to create a Design Unit? Interface to environment (ENTITY) Design Unit Functionality (ARCHITECTURE) Each Design Unit consists of one ENTITY and no, one or more ARCHITECTUREs 3
4 ENTITY Declaration 4 Interface of a block to the environment Name of the block Inputs and outputs (ports) Additional declaration of parameters possible (generics) No functional descriptions Comparable to a schematic symbol of a component
5 ENTITY Example Example of a half adder Schematic symbol entity name entity half_adder is port port mode (direction) port name ( port type a, b : in bit; carry, sum : out bit ); end entity half_adder; a b sum carry 5
6 Generics Example 6 Adder with configurable bus width entity adder is generic ( WIDTH : integer := 8 ); port ( a, b : in bit_vector (WIDTH - 1 downto 0); sum : out bit_vector (WIDTH - 1 downto 0); carry : out bit ); end entity adder;
7 Port Types Read Write Comment in X - out (X) X Read in VHDL 2008 inout X X buffer X X Can only be written by one source 7
8 Architecture Describes the functionality of a design unit The functionality can be described on different levels Y-diagram, will be discussed in future lecture Mixing of different levels possible No, one or multiple architectures for each entity possible 8
9 Architecture Example architecture name entity name 9 loop architecture rtl of half_adder is begin process(a,b) begin if a=`1` and b=`1` then carry <=`1`; sum <=`0`; elsif a /= b then carry <=`0`; sum <=`1`; else carry <=`0`; sum <=`0`; end if; end process; end architecture rtl; sensitivity list
10 Configuration (1) One entity could have multiple architectures The assignment of the currently active one is done by a configuration Entity Configuration Architecture 1 Architecture 2 Architecture 3 Advantage: Different implementation of an entity can exist in parallel and be switched by only changing the configuration. 10
11 Configuration (2) configuration name entity name configuration half_adder_cfg of half_adder is for rtl end for; end configuration half_adder_cfg; 11
12 Configuration (3) a AND sum Architecture 1 Architecture 2 b XOR carry Architecture 1 Architecture 2 configuration half_adder_cfg of half_adder is 12 for rtl end for; end half_adder_cfg ; for and : and_gate use work.and_gate(behaviour); for xor : xor_gate use work.xor_gate(structure); additional configurations entity of instance architecture of instance instance name, Keyword all configures all instances of the specified entity
13 Design Unit Design unit consists of One entity, No, one or multiple architectures And an optional configuration! Entity Config Architecture The three components can be in separate files or in a common one entity half_adder is port ( a, b : in bit; carry, sum : out bit ); end entity half_adder; configuration half_adder_cfg of half_adder is for rtl end for; end configuration half_adder_cfg; architecture rtl of half_adder is begin process(a,b) if a=1 and b=1 then carry <=`1; sum <=`0`; elsif a<> b then carry <=`0`; sum <=`1`; else carry <=`0`; sum <=`0`; end if; end process; end architecture rtl; 13
14 Package (1) Project1 Project 2 Components can be grouped in packages By using the package they can be used in multiple projects Package Comparable to C header files Entity D Entity A Entity B Entity C 14
15 Package (2) 15 A package can be used in multiple projects It can contain: Custom data types, Component declarations, Function and procedures Constants... A package consists of Package declaration Package Body (Implementation of function and procedures)
16 Libraries Libraries contain (precompiled) VHDL Units Libraries have to be made visible by library lib_name; The library directive can be used before an entity, architecture, configuration, package or package body 16
17 USE - Clause Makes elements of a library visible use ieee.numeric_std. + element name library name package name Instead of the element name.all can be used to make all elements of the library visible. 17
18 Library work Standard library for your compiled designs Library work always visible No library clause required Custom packages normally in this library Packages have to be made visible with use clause 18
19 Standard Library (std) 19 Defined in IEEE-1076 standard Contains the packages standard und textio Package standard (always visible, no use clause required) Defines Basic types: bit, boolean, integer, natural, Operations for the basic types: and, or, not, =, /=,<, Package textio (not visible by default, use clause required) Defines text mode file operations
20 Library ieee (1) Package std_logic_1164: Types std_logic, std_ulogic,... Operators and, or, not,... Conversion functions: e.g.: to_bit, to_stdlogic,... Other functions rising_edge, falling_edge, 20
21 Library ieee (2) 21 Package numeric_std: Types signed unsigned Operators +, -, *, /, ABS,... <, >, <=,... Conversion functions to_integer(arg : unsigned) return integer... Synopsys version: std_logic_arith Not standard => do not use!
22 Conclusion (1) A design unit consists of: Architecture 1 Entity Configuration Architecture 2... Architecture n 22
23 Conclusion (2) Design Units can be grouped in packages (component declarations) Packages can also include constants, type declarations, procedures and functions Design units/packages can be grouped in libraries 23
24 Conclusion (3) A library must be made visible: library my_lib Elements of a library must be imported: use my_lib.adder_pkg.half_adder; Special cases Library work (always visible) Package std.standard (always visible).all (all elements of a package) 24
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