[1] Douglas L. Perry, VHDL, third edition, ISBN , McRaw- Hill Series on Computer Engineering.
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1 Lecture 10 1 Reference list [1] Douglas L. Perry, VHDL, third edition, ISBN , McRaw- Hill Series on Computer Engineering. [2] Kevin Skahil, VHDL for programmable logic, ISBN Addison-Wesley. [3] David Pellerin, Douglas Taylor, VHDL Made Easy, ISBN Prentice Hall. [4] Ben Cohen, VHDL Answers to Frequently Asked Question, 2nd edition, ISBN , Kluwer Academic Publishers. [5] Sudhakar Yalamanchili, Introductory VHDL Simulation to Synthesis, ISBN , Prentice Hall. [6] Digital design with Hardware Description Languages, Mark Davidson, Jyrki Alamaunu, Tommi Zetterman, Autum [7] Peter J Ashenden, The Student s Guide to VHDL, ISBN Morgan Kaufmann Publishers, Inc, San Francisco California, [8] DIGITAL INTEGRATED CIRCUITS a design perspective, second ed., Jan M. Rabaey, Anantha Chandrakasan, Borivoje Niklic', Prentice Hall, ISBN [9] Digital Design, Prinsiples and Practices, fourth ed., John F. Wakerly ISBN
2 Our goal of these slides is to construct models of digital systems for simulation and synthesis. 3 Entity declaration An entity is most basic building block in a design. Schematic symbol Entity declaration eqcomp4 a[3:0] equals b[3:0] Symbol for 4-bit comparator entity eqcomp4 is port (a, b : in bit_vector(3 downto 0) ; equals : out bit ) ; end eqcomp4 ; -----VHDL 1987 entity eqcomp4 is port (a, b : in bit_vector(3 downto 0) ; equals : out bit ) ; end entity eqcomp4 ; -----VHDL 1993 [2]p.107 [5]p.50 4
3 Entity declaration Example 1 : RS flip-flop ENTITY rsff IS PORT ( set, reset : IN BIT ; q, qb : BUFFER BIT ) ; END rsff ; -----VHDL 1987 [1]p.5 5 Entity declaration Syntax for simpilified form of entity declaration entity identifier is [ port (port_interface_list) ; ] {entity_declarative_item} end [entity] [identifier] ; You can set the default value of input if it is left unconnected. interface_list <= (identifier {, }: [mode] subtype_indication [ := expression]) {, } mode <= in out inout Full syntax description : see reference [4] page 344 [7]p.104 6
4 Entity declaration Generics in entity declaration Models can be tuned using generics. entity AndGate_Nty is generic ( DlyIO_g : time := 4 ns ) ; port (I1 : in bit ; I2 : in bit ; O : out bit ) ; end entity AndGate_Nty ; architecture AndGate_a of AndGate_Nty is begin O <= I1 and I2 after DlyIO_g ; end AndGate_a ; [7] p [4]p.26 [4]p Entity Design entity is a pairing of an entity declaration and an architecture body. Schematic equivalents. [1]p.6 p.7 [2]p.107 8
5 Entity All entities that can be simulated have an architecture description. An architecture body describes the function of a design entity. A single entity can have multiple architectures. Different abstraction levels. [1]p.3 [2]p PORT clause in entity declaration ENTITY entity_name IS PORT (port_name1, port_name2 : mode type ; port_name3, port_name4 : mode type ) ; END ENTITY entity_name ; PORT clause Describes the inputs and outputs of design entity Mode of the inputs and outputs. Signal types of the inputs and outputs [2]p
6 PORT clause in entity declaration Each port you declare must have a name (identifier) a direction (mode) and a data type [2]p PORT mode Mode describes the direction in which data is transferred through port. In Out Buffer In In Inout Out [2]p
7 PORT mode In Data flows only into the entity. The driver for a port is external to the entity. Out Data flows only from its source to the output port of the entity. The driver for a port is inside the entity. Mode out does not allow for feedback. [2]p PORT mode Buffer Port is similar to a port that is declared as mode out, except that is does allow for internal feedback. Mode buffer does not allow for bidirectional ports. Mode does not permit the port to be driven from outside of the entity. [2]p
8 PORT mode Buffer Note! A port of mode buffer may not be multiply driven. A port of mode buffer may connect only to an internal signal or to a port of mode buffer of another entity. [2]p PORT mode Examble 2 Buffer A port of mode buffer in FSM design. Finite State Machine [2]p
9 PORT mode Inout Bidirectional signals Allows data to flow into or out of the entity. Signal driver can be inside or outside of the entity. Port Allows internal feedback. [2]p PORT mode Inout Note! Mode inout can replace any of the other modes, but.. It makes difficult to discern the source of signals. Use mode inout for signals that are truly bidirectional. [2]p
10 PORT mode Inout, Out and Buffer Note! In synthesis, ports of direction out, inout and buffer have NO correlation with the implemented hardware drivers. (push-pull, open collector, tri-state diver) The hardware driver is determined by the values of the signals supplied to the ports and by the directed technology. [4]p.17,18 19 PORT mode Inout, Out and Buffer Note! If a 'Z is assigned onto a port, the synthesizer will implement a tri-state or open-collector hardware driver. If only forcing values ( '0 ', '1 ' ) are assigned, with no 'Z ', then push-pull type of hardware driver will most likely be implemented. [4]p.17,18 20
11 The basic identifier VHDL language is not case sensitive. The first character must be a letter The basic identifier The last character cannot be an underscore. Two underscores in succession are not allowed. [2]p The basic identifier Identifier Legal names Not legal names why? tx_clk _tx_clk must start with letter Three_state_Enable 8B10B must start with letter sel17d large#number letter, digits, underscores only HIT_1124 link bar two underscores not allowed select reserved word rx_clk_ last character cannot be underscore [2]p
12 Object An object has in a VHDL model a value of a specified type. There are 4 classes of objects. 1. Constants 2. Variables 3. Signals 4. Files [6] 23 Constants and Variables Constants and Variables are objects which can STORE data for use in model. Note! The value of a constant can not be changed after its creation. Variables can change value using variable assignment. [6] 24
13 Constants Syntax for the constant declaration constant identifier {,.} : subtype_indication [ := expression ] ; Examples constant number_of_bytes : integer := 4; constant e : real := ; constant prop_delay : time := 3 ns; [6], [4]p Variables Syntax for the variable declaration variable identifier {,.} : subtype_indication [ := expression ] ; Examples : variable index : integer := 0; variable start, finish : time := 0 ns ; [6], [4]p
14 Variables Syntax for the variable assignment [label :] target := expression ; Example : Program_counter := 0 ; [6], [4]p Variables Note! Variables can be declared in the process declaration section and subprogram declaration sections only. Variables are used for local storage in process statements and subprograms. Visible only inside a process. [1]p.69, 72 28
15 Variables Example architecture behav of reg4 is begin storage : process is variable stored_d0, stored_d1 : bit ; variable stored_d2, stored_d3 : bit ; begin if en= 1 and clk= 1 then stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3; end if ; q0 <= stored_d0 after 5ns ; q1 <= stored_d1 after 5ns ; q2 <= stored_d2 after 5ns ; q3 <= stored_d3 after 5ns ; wait on d0, d1, d2, d3, en, clk ; end process storage ; end architecture behav ; [6] 29 Signals Be aware of differences between signals and variables! Variable assignments immediately overrides the variable with a new value. The signal is visible between processes while variable is not. Thus signal must be used to pass data. The signal objects are used to connect entities together to form models. More information in ref. [4]p.304 and [1] chapter 4. [6], [1]p.69 30
16 Signals Syntax for the signal declaration signal identifier {,.}: subtype_indication[signal_kind][:=expression]; Examples register bus [3]p.320,345 signal a : real ; signal Reset : Std_uLogic := 0 ; signal InternalReg_s : bit ; signal Data : Std_Logic_Vector(2 downto 0) ; [4]p.288, 349, [3]p.320, Signals Syntax for the signal assignment (VHDL1993) [label :] target <= [delay_mechanism] waveform ; value_expression [after time_expression] Note! Not complete syntax description. See detailed information from ref. [4]p.349- [4]p.349,
17 Signals Examples sys_clk <= not(clk_1) after 5 ns ; a <= 1.0 ; a <= 4 ; Error, must be real InternalReg_s <= 1 ; 33 Signals Signal visibility It depends where signals are declared. Entity declaration Architecture declaration Package declaration Global signals Global signals are declared in packages. Those signals are made visible in any architecture that makes the library accessible to the architecture (use clause). [4]p.285 [1]p.71 34
18 Signals Signal visibility Signals global to entities Signals are declared inside the entity declaration section. Signal can be referenced in that entity and any of architecture for entity. [1]p Signals Signal visibility Architecture local signals Signal is declared in the architecture declaration section. Signal can be referenced only in that architecture or in any process statements in the architecture. [1]p.71 36
19 The End 37
[1] Douglas L. Perry, VHDL, third edition, ISBN , McRaw- Hill Series on Computer Engineering.
![[1] Douglas L. Perry, VHDL, third edition, ISBN , McRaw- Hill Series on Computer Engineering.](/thumbs/78/78365055.jpg "[1] Douglas L. Perry, VHDL, third edition, ISBN , McRaw- Hill Series on Computer Engineering.")
Lecture 12 1 Reference list [1] Douglas L. Perry, VHDL, third edition, ISBN 0-07-049436-3, McRaw- Hill Series on Computer Engineering. [2] Kevin Skahil, VHDL for programmable logic, ISBN 0-201-89586-2
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