What Is VHDL? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE 1076 standard (1987, 1993)

Transcription

1 What Is VHDL? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE 1076 standard (1987, 1993) Only possible to synthesize logic from a subset of VHDL Subset varies according to software

2 VHDL Styles Abstraction defines details Behavioral describe function without defining architecture; timing detail as required RTL defines every register and logic in between; cycle based timing Logic interconnect logic gates and registers; detailed timing Layout actual layout of the design on silicon; may specify detailed timing and analog effects

3 Main Language Concepts Hierarchy describe structure using varying styles Concurrent describe hardware operating in parallel Sequential statements that execute one after another Time VHDL allows time to be modeled

4 Entity the main building block Describes the interface to a hierarchical block entity HALFADD is port (A,B : in bit; SUM,CARRY : out bit); end HALFADD; Equivalent to a symbol in schematic design

5 Architecture describe entity behaviour architecture BEHAVE of HALFADD is begin SUM <= A xor B; CARRY <= A and B; end BEHAVE;

6 Hierarchy Hierarchy is built from entities and architectures Example full adder built from two half adders and an OR gate

7 Example full adder entity entity FULLADD is port (A, B, CIN : in bit; SUM, CARRY : out bit); end FULLADD; Build the full adder based on entity HALFADD is port (A,B : in bit; SUM, CARRY : out bit); end HALFADD;

8 Example full adder architecture architecture STRUCT of FULLADD is signal I1, I2, I3 : bit; -- other declarations begin u1:halfadd port map(a,b,i1,i2); u2:halfadd port map(i1,cin,sum,i3); CARRY <= I2 or I3; end STRUCT; Local signals Local to the architecture; not inputs or outputs Declared in the architecture before the begin

9 Declarations components architecture STRUCT of FULLADD is signal I1, I2, I3 : bit; component HALFADD port(a,b : in bit; SUM, CARRY : out bit); end component; begin u1:halfadd port map(a,b,i1,i2); u2:halfadd port map(i1,cin,sum,i3); CARRY <= I2 or I3; end STRUCT;

10 Example - fulladder entity FULLADD is port (A, B, CIN : in bit; SUM, CARRY : out bit); end FULLADD; architecture STRUCT of FULLADD is signal I1, I2, I3 : bit; component HALFADD port(a,b : in bit; SUM, CARRY : out bit); end component; begin u1:halfadd port map(a,b,i1,i2); u2:halfadd port map(i1,cin,sum,i3); CARRY <= I2 or I3; end STRUCT;

11 Configurations A design hierarchy consists of a set of entities, each of which can have multiple architectures. The configuration specifies which architecture will be used for each entity. For some software, the last architecture compiled will be used for the entity.

12 Configurations configuration CFG_A of A is for X end for; end CFG_A; Configuration has a name and is associated with the top entity in the hierarchy. For example, entity A will use architecture X.

13 Processes entity ORGATE is port (A,B : in bit; Z : out bit); end ORGATE; architecture BEHAVE of ORGATE is begin OR_FUNC: process (A,B) begin if (A='1' or B='1') then Z <= '1'; else Z <= '0'; end if; end process OR_FUNC; end BEHAVE;

14 Packages A package contains a collection of definitions that may be referenced by many designs; acts like a subroutine library. A package is a separate design unit and therefore exists outside of other design units (entity, architecture, configuration). A package can have two parts: declaration and body.

15 Packages - structure package PROJECT_X is -- constants -- user defined types -- component declarations -- sub programs end PROJECT_X;

16 How source code is compiled VHDL code is written as a text file with name name.vhd The file is compiled (checked for syntax errors and binary created). The smallest unit that can be compiled is a single design unit: entity, architecture, configuration, package declaration, package body. (These 5 units are the only design units in VHDL.)

17 Data types Every signal must have a data type when it is declared (strong typing). Assignment to that signal must be of the same type. For example, SUM must be of the same type as A xor B. SUM <= A xor B;

18 Data types entity FULLADD is port (A,B,CIN : in bit; SUM, CARRY : out bit); end FULLADD; architecture STRUCT of FULLADD is signal N_SUM : bit; -- other declarations begin -- Code end STRUCT;

19 Predefined data types The standard types predefined in VHDL are: Bit ( 0, 1 ); Bit_vector (e.g ) Boolean (true, false) Character (ASCII set; a ); String ( abd ) Integer (range implementation dependent; 123) Real (range implementation dependent;123.0) Time (number and unit; 10 ns)

20 Signals and Drivers A signal is assigned a new value with a signal assignment statement. Z <= A; An assignment to a signal defines a driver on that signal. The concept of a driver is the same as an output of a logic gate drives a signal in real hardware.

21 Signals and Drivers If more than one assignment is made to a signal Z <= A; Z <= B; then that signal has more than one driver. In this case, the signal must be of type resolved. A resolved type has a function call associated with it to resolve the final value of the signal. Since all types discussed so far are unresolved types, the example above is illegal.

22 Arrays The range of an array is defined when the array is declared. signal A_BUS: bit_vector (7 downto 0); signal B_BUS: bit_vector (0 to 7); An array may be assigned to another array of the same type and size. A_BUS <= B_BUS; Note that assignment is by position not index number. VHDL has no concept of a most significant bit.

23 Array slice A slice of an array may be referenced. signal Z_BUS: bit_vector (3 downto 0); signal A_BUS: bit_vector (1 to 4); Z_BUS (3 downto 2) <= 00 ; C_BUS (2 to 4) <= Z_BUS(3 downto 1); Slice direction must match declaration direction. Z_BUS (2 to 3) <= 00 ; -- illegal

24 Concatenation signal Z_BUS : bit_vector(3 downto 0); signal A, B, C, D : bit; signal BYTE : bit_vector(7 downto 0); signal A_BUS: bit_vector(3 downto 0); signal B_BUS: bit_vector(3 downto 0); Z_BUS <= A & B & C & D; BYTE <= A_BUS & B_BUS; Concatenation operator is &

25 Aggregates Assignment by position: signal Z_BUS : bit_vector(3 downto 0); signal A, B, C, D : bit; Z_BUS <= (A, B, C, D); Assignment by name: X <= (3=>'1', 1 downto 0=>'1', 2 => B); Aggregates can use the others statement: X <= (3=>'1', 1=>'0', others => B);

26 User defined type Enumerated type (encoding left to right in binary sequence): type MY_STATE is (RESET, IDLE, RW_CYCLE, INT_CYCLE);... signal STATE : MY_STATE; signal TWO_BIT : bit_vector (0 to 1);... STATE <= RESET; STATE <= 00 ; -- illegal STATE <= TWO_BIT; -- illegal