Programmable Logic Design Grzegorz Budzyń Lecture. 4: Introduction to VHDL
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1 Programmable Logic Design Grzegorz Budzyń Lecture 4: Introduction to VHDL
2 Plan History Main features Building blocks: Entity Architecture body Package Configuration declaration
3 History
4 Some history The name: VHSIC (Very High Speed Integrated Circuits) Hardware Description Language Important dates: 1983: development started with support from US government. 1987: adopted by IEEE as a standard (IEEE Std ). 1993: VHDL 92 adopted as a standard after revision of the initial version (IEEE Std ).
5 VHDL main features
6 Main features Supports the whole design process: system level RT level (Register Transfer) logic level circuit level (to some extent) Suitable for specification in behavioral domain(behavioral modeling) structural domain(structural modeling) Precise simulation semantics is associated with the language constructs
7 Main features VHDL is the Hardware Description Language: FPGAs do NOT contain a hidden microprocessor or interpreter or memory that executes the VHDL or Verilog code Synthesis tools prepare a hardware design that is inferred from the behaviour described by the HDL A bit stream is transferred to the programmable device to configure the device No shortcuts! Necessity to understand combinational/sequential logic
8 Behavioral modeling Circuit is described only by its functionality Hardware elements are not taken into consideration Source: [2]
9 Structural modeling Circuitisdescribedwitha viewon a possible construction Source: [2]
10 RTL Synthesis Source: [2]
11 Basic constructs The basic building block of a VHDL model is the entity An entity is described as a set of design units: entity declaration architecture body package declaration package body configuration declaration
12 Basic constructs A digital component is described using an: ENTITY DECLARATION ARCHITECTURE BODY PortsarelikeIC pins, connectedby wires called SIGNALS Main enumeration type used is STD_LOGIC
13 Basic constructs Therearetwoset ofconstructs: Synthesis Simulation VHDL is case insensitive Comments are preceded by two consecutive dashes. --commentendsattheendofcurrentline VHDL statements are terminated with; VHDL is white space insensitive for better readability
14 VHDL Program structure
15 Program structure Source: [1]
16 Program structure
17 Building blocks - entity Every portion of a VHDL design is considered a block A VHDL design may be completely described in a single block, or it may be decomposed in several blocks. Each block in VHDL is analogous to an off-theshelf part and is called an entity. Ports are the communication links between entities or connection to the device pins
18 Building blocks - entity The entity describes the interface to that block A separate part associated with the entity (architecturebody)describes how that block operates. The interface description specifiesthe inputs and outputs to the block. The description of the operation of the part is like a schematic for the block.
19 Building blocks - entity
20 Building blocks entity: generic Genericsare a means of passing specific information into an entity Generics instance example
21 Building blocks architecture body The architecture body describes how the design operates(defines the function or behaviour of the entity) Consists of concurrent statements e.g: Process statements Concurrent Signal Asignment statements Conditional Signal Asignment statements An entity may have several architectures
22 Building blocks architecture body Architecture MUST be associated with an entity Entity can have multiple architectures Architecture processes are executed concurrently Architecture styles: Behavioral(how design operates) Structural(netlist) Hybrid
23 Building blocks architecture body
24 Building blocks architecture body
25 Architecture body components A component is analogous to a chip socket. Itcreates an extra interface which allowsmore flexibility when building hierarchicalsystem out of its component parts.
26 Architecture body components Source: [1]
27 Building blocks configuration A VHDL description may consist of many design entites, each with several architectures(organized into a design hierarchy) The configurationisusedforspecifying the exact set of entities and architectures used in a particular simulation or synthesis run
28 Building blocks configuration A configuration does two things: specifies the design entity used in place of each component instance specifies the architecture to be used for each design entity
29 Building blocks configuration Widely used in simulation environment Provides a flexible path to design alternatives Limited or no support for synthesis
30 Example 1/2:
31 Example 2/2:
32 VHDL Ports& data types
33 Architecture body Port modes In VHDL there are fourmodesoftheports: in : input into the entity ( unidirectional) out : output from the entity( unidirectional) inout: input and output to and from the entity( bidirectional signals ) buffer : behaves in a similar way as inout,but the source of the buffered signal is alwaysdetermined by the driving value of the port.
34 Architecture body Data types In VHDL there are many scalar and array data types
35 Architecture body Data types
36 Architecture body Data types
37 Architecture body Data types
38 Architecture body Data types
39 Architecture body Data types
40 Architecture body Data types
41 Architecture body Data types
42 VHDL Signals& Variables
43 Architecture body signal An internal connection is described in VHDL as a signal defined inside the architecture
44 Architecture body variable Variables can be pieces of wire too, but they are usually more abstract. Variables can represent wires, registers, or be used tostore intermediate values in abstract calculations. Variables must be defined inside a process, before begin (unlike signals which are defined in an architecture).
45 Signals vs variables Bothareusedto holddata Signalisused mostly in structural and data flow descriptions Varaiblecan onlybe used in processes A variable behaves like in a software programming language, which is much different than the behavior of a signal
46 Signals vs variables Although variables represent data like the signal, they do not have or cause events and are modified differently Variables are modified with the variable assignment The valuesaresimply copied to avariable immediately
47 Signals vs variables Assignments may be made from signals to variables and vice-versa, providing the types match A variable assignment may not be given a delay A variable in a process can act as a register, if it is read before it has been written to, since it retains its value between sucessive process activations
48 Variables synthesis issues Variable assignments are generally synthesisable, providing they use types and operators acceptable to the synthesis tool In a "clocked process", each variable which has its value read before it has had an assignment to it will be synthesisedas the output of a register In a "combinational process", reading a variable before it has had an assignment may cause a latch to be synthesised Variables declared in a subprogram are synthesised as combinational logic
49 VHDL Process
50 Architecture body concurrent statement It is a statement which execute inparallel with other concurrent statements in the design hierarchy. They are written between begin and end in an architecture. The most common concurrent statements are a) the process b) the component instantiation c) concurrent signal assignment
51 Architecture body process Themainpart ofthearchitecturebody isa process: a process can be viewedas a sequential program, a processisa sequenceofstatements each process is a single concurrent statement processes are run in parallel, the process can be suspended (wait statement) and reactivated by receiving a signal or timing condition a processcommunicateswiththerestofa design via signals or ports defined outside the process
52 Architecture body process A process is an operation that involves a number ofparameters identified in a sensitivity list: Proc_x: part is optional
53 Architecture body process A process implements a sequential algorithm: Evaluation of the statements inside the process is sequential, i.e. top to bottom Multiple assignments to the same signal may exist Thelastassignmentbeforetheendoftheprocess is the real assignment SequentialstatementsMUSTresidewithina process
54 Architecture body process A process is activated when defined signals change state: Monitored signals defined in sensitivity list or Monitored signals listed in WAIT statements A process is either being executed or suspended. It isexecuted when one of the signals in its sensitivity list had an event, a change of value. The process continues to execute until the last statement isreached or it encounters a wait statement. It then suspends itself.
55 Architecture body process A processcanbe definedwithoutany sensitivity list: theseprocessesmust haveatleastone WAIT statement The WAIT statement defines signals that are monitored for change Non-sensitiveprocessesareactivatedwhenWAIT statement signals change state Process suspends when next WAIT statement is encountered
56 Architecture body process ACTUAL SIGNAL ASSIGNMENTS ARE ONLY MADE AT THE END OF PROCESS EVALUATION!!!
57 VHDL program structure (more complete) Source: [1]
58 VHDL packages& libraries
59 Architecture body package VHDL packages are collections of reusable declarations and descriptions of VHDL types, subtypes, subprograms, aliases, constants, attributes, components, etc. Packageencapsulateselementsthatcanbe globallysharedamongtwoormoredesign units
60 Architecture body package A packageconsistsoftwoparts:
61 Architecture body package Packagescanbe madeby theuser Usually with the compiler there are installed many useful packages:
62 Packages - example
63 Libraries Librarycontaina packageora collectionof packages Resource Libraries: Standard Package IEEE developed packages Anylibraryofdesign unitsthatarereferencedina design Working Library: Libraryintowhichtheunit isbeingcompiled
64 Referencing Libraries/Packages All packages must be compiled Implicitlibraries(do not needto be referenced) WORK andstd LIBRARY clause: Defines the library name that can be referenced Is a symbolic name to path/directory USE clause: Specifies the package and object in the library
65 Referencing example
66 Types defined in STD package TypeBIT: 2 logicvaluesystem ( 0, 1 ) BIT_VECTOR also possible Type BOOLEAN: (false, true) Type INTEGER: Positive and negative values
67 Types defined in STD package Type NATURAL: Positive integer from 0 Type POSITIVE Type CHARACTER: ASCII characters Type STRING: Array of characters TypeTIME: Unitsoftime(e.g. ps, us, ns, ms, sec, min, hr)
68 IEEE package elements The package std_logic_1164 provides enhanced signal types: Types defined include: std_ulogic std_ulogic_vector std_logic std_logic_vector The package std_logic_textio provides input/output for 1164 types Functions defined include: readline read writeline write endline
69 IEEE package elements The package math_real provides numerical computation on type real The package math_complex provides numerical computation Types defined include: complex, complex_vector, complex_polar
70 IEEE package elements The package std_logic_signed provides signed numerical computationon type std_logic_vector The package numeric_std provides numerical computation Types defined include: unsigned signed arrays of type std_logic for signals
71 VHDL tips& tricks
72 VHDLs tips & tricks Thereisno explicitreferenceto actual hardware components: There are no D-type flip-flops, mux, gates etc. RequiredlogicisinferredfromVHDL description Same VHDL can target many different devices
73 VHDLs tips & tricks Therearemany alternativewaysto describe the required behaviour of the final system: Exactlythesame hardware will be produced(?) Somewaysaremoreintuitiveandeasierto read
74 VHDLs tips & tricks Itisimportantto be awarethatthe synthesistoolsmustbe ableto deducethe intentoftheauthorandsystem requirements: For sequentialsystemsitisusuallynecessaryto follow recommended templates and style
75 Thank you for your attention
76 References [1] Krzysztof Kuchcinski, Introduction to VHDL [2] Altera, On line VHDL course [3] [4] ocess_vhdl.ppt#285,20,combinational Logic Processes(cont.)
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