ECE251: Tuesday Aug. 29

Transcription

1 ECE251: Tuesday Aug. 29 ARM Cortex Architecture: Data Movement Loading memory data into registers Storing register data into memory Indexed Addressing Reading: Chapters 1 and 5 Labs: #1 due this week at beginning of your lab. Do Lab #2 this week and next; Prework is due at the beginning of your Lab 2! Lab #2 due 2 weeks later. HW #1 Due Sept. 7, 4 p.m. in BC Infill Lecture #3 1

2 Just for Fun (Do you want to see more of these?) Lecture #3 2

3 TA and Grader Office Hours Joel: Monday 1:00 to 2:00 Aaron: Thursday 3:30 to 4:30 Two Choices for Marcus: Vote ONLY if you have a conflict with Joel s hours! Monday 3:30 to 4:30 Tuesday 1:00 to 2:00 Lecture #3 3

4 Data Types and Memory By grouping bits together we can store more than a single bit at a time: 8 bits = 1 byte 16 bits = 2 bytes = 1 halfword 32 bits = 4 bytes = 1 word From software perspective, memory is an addressable array of bytes, The byte stored at the memory address 0x is 0b Or [0x ] = 0b Content of hex is binary b = 0x84 = 132 Binary Hexadecimal Decimal Lecture #3 4

5 Data Storage Constraints When we refer to memory locations by address, we only do so in units of bytes, halfwords or words Words 32 bits = 4 bytes = 1 word = 2 halfwords In diagram to right, we have two words: At addresses 0x and 0x Can you store a word/halfword anywhere? NO. A word can only be stored at an address that's divisible by 4. A halfword is stored at an address that s divisible by 2. Memory address of a word/halfword is the lowest address of all four bytes in that word. High Address 0x x x x x x x x Low Address 8 bits Lecture #3 5

6 Endianness Big Endian: address of most significant byte = word address Little Endian: address of least significant byte = word address ARM is Little Endian by default. Little Address, Little Byte 0x : More than enough said. Not critical to ECE251, but who knows when a corporate recruiter might ask you about this! Lecture #3 6

7 ARM Cortex Instructions ARM comes in lots of versions, evolving since 1983: Acorn RISC Machine Advanced RISC Machine RISC is Reduced Instruction Set Computing (~1980) Our textbook describes ARM M3/M4 version and STM I/O TM4C123G uses ARM M4 version and TI I/O ARM differences are only enhancements in M4 But I/O differs significantly (which will be documented as needed) We will use the better board (TI) and the better text (Zhu) for our purposes! And all this stuff is thoroughly modern, state of the art! Lecture #3 7

8 ARM Cortex Instructions See class web references and summaries (below) to Syntax (form or structure) and Semantics (behavior) of all ARM Cortex-M4 instructions. Cortex M3/M4F Instruction Set, 221 pages Cortex M4 Generic User Guide, Chapter 3, 169 pages Quick Reference Card, summary, 6 pages Cortex Instruction Encoding, two appendices of text Instruction encoding is the pattern of 1 s and 0 s representing each instruction Quick Reference Card will be available to you on exams and practical exams Lecture #3 8

9 ARM Instructions, Major Groups Data Movement Load Store Move Arithmetic and Logic Add and Subtract Multiply and Divide Shift and Rotate Compare and Branch Compare, Test Branch Miscellaneous Wait for events Interrupts Many others Lecture #3 9

10 ARM Assembly Language label mnemonic operand1, operand2, operand3 ; comments Loc ADD R3, R2, R1 ; R2+R1 R3 Label is a symbolic reference to this instruction s address in memory. Mnemonic represents the operation to be performed. The number of operands varies, depending on each specific instruction. Some instructions have no operands at all. operand1 is typically the destination register, and operand2 and operand3 are source operands. operand2 is usually a register. operand3 can represent many different things, depending on instruction. Everything after the semicolon is a comment, which is ignored by the assembler. We will discuss this in more detail later. This is just to get us going. Lecture #3 10

11 Load-Modify-Store Example (just for fun) Algebraic statement x = x + 1 ; Assume the x is stored in memory and the ; memory address of x is stored in r1 LDR r0, [r1] ; load value of x from memory ADD r0, r0, #1 ; x = x + 1 # means immediate STR r0, [r1] ; store new value of x into memory Lecture #3 11

12 Load/Store Instructions, for example Load instruction : LDR rt, [rs] Fetch word from memory and put into register rt. The memory address is specified in register rs. For Example: ; Assume [r0] = 0x ; Load a word: LDR r1, [r0] ; [0x :0x ] r1 Very similar for Store instruction: STR STR r1, [r0] ; [r1] 0x :0x Note that these are both word (4-byte) instructions Lecture #3 12

13 Types of Load and Store Instructions We just did these What are these Signed loads about? Lecture #3 13

14 Data Movement Instructions Memory Access (See Chapter 5) To access memory, first establish a register pointing to the object. This pointer (called an index) is then used in a Load (LDR) or Store (STR) instruction (or both). Load word from memory into a register E.g. Somehow make [r5] = 0x LDR r2, [r5] will place the 4 bytes starting at address 0x into register 2: [0x :23] r2 Very very common instruction Store word from register into memory STR r3, [r5] ;will place register 3 contents (4 bytes) into addresses 0x :0x (see previous example) Very common instruction Lecture #3 14

15 Indexed Load Example Address of the data in memory is in a register shown below with [R1] = 0x , [PC]=0x144, and [0x144]= 0x6808 [0x ] = Brackets below denote use of register as index to reference memory LDR R0,[R1] ; R0 = value pointed to by R1 PC R0 R1 0x x EEPROM 0x x LDR R0,[R1] 0x x x RAM 0x x x x C Lecture #3 15

16 Indexed Load and Store Instructions These are important to understand! Can include an offset from the index address Can include updating index register with offset (pre- or post- access) General load/store instruction format LDR{type} Rd,[Rn] STR{type} Rt,[Rn] LDR{type} Rd,[Rn, #n] STR{type} Rt,[Rn, #n] ;load memory at [Rn] to Rd ;store Rt to memory at [Rn] ;load memory at [Rn+n] to Rd, Rn unchanged ;store Rt to memory [Rn+n], Rn unchanged LDR{type} Rd,[Rn,Rm,LSL #n] ;load [Rn+Rm<<n] to Rd, Rn unchanged STR{type} Rt,[Rn,Rm,LSL #n] ;store Rt to [Rn+Rm<<n], Rn unchanged LDR{type} Rd,[Rn, #n]! STR{type} Rt,[Rn, #n]! LDR{type} Rd,[Rn], #n STR{type} Rt,[Rn], #n ;load memory at [Rn+n] to Rd, update Rn ;store Rt to memory [Rn+n], update Rn ;load memory at [Rn] to Rd, update Rn ;store Rt to memory [Rn], update Rn Next time (or today, if we have time), we ll do several examples with these Loads and Stores Lecture #3 16

17 {type} for Index Addressing e.g. LDR{type} Rd,[Rn] ;load memory at [Rn] to Rd {type} Data type Meaning 32-bit word 0 to 4,294,967,295 or -2,147,483,648 to +2,147,483,647 B Unsigned 8-bit byte 0 to 255, Zero pad to 32 bits on load SB Signed 8-bit byte -128 to +127, Sign extend to 32 bits on load H Unsigned 16-bit halfword 0 to 65535, Zero pad to 32 bits on load SH Signed 16-bit halfword to , Sign extend to 32 bits on load D 64-bit data Uses two registers Lecture #3 17

18 Pre-indexed Load Example Pre-Index: LDR r1, [r0, #4] r0=0x Offset range is -255 to +255 Lecture #3 18

19 Post-indexed Load Example Post-Index: LDR r1, [r0], #4 r0=0x Offset range is -255 to +255 Lecture #3 19

20 Pre-indexed Load with Update Pre-Index: LDR r1, [r0, #4]! r0=0x Offset range is -255 to +255 Lecture #3 20

21 All about memory Today s Summary Data types and storage Loading and storing data Using index addressing With or without offsets With or without updating index register VERY IMPORTANT CONTENT Learn this! Read Chapter 5 of text and UNDERSTAND IT Next Lecture(s): More examples, then Add/Subtract & Multiply/Divide Shift/Rotate, Bitwise Logic, Saturating Instructions Lecture #3 21