EE University of Minnesota. Midterm Exam #1. Prof. Matthew O'Keefe TA: Eric Seppanen. Department of Electrical and Computer Engineering

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1 EE Uiversity of Miesota Midterm Exam #1 Prof. Matthew O'Keefe TA: Eric Seppae Departmet of Electrical ad Computer Egieerig Uiversity of Miesota Twi Cities Campus EE 4363 Itroductio to Microprocessors 23 February 2009 Aswer all questios. There is a total of 100 poits ad you should have 9 pages i your test. Please place your ame, ID umber ad recitatio umber i the space below. Please: do it ow. Remider: This test is closed book ad closed otes; o calculators are allowed. Show ALL your work. Additioal pages are provided at the ed of the exam. There are also copies of the gree card (both sides) from your book, as well as figures 2.19 ad 2.20 from the book. The latter two figures will assist you with decodig a biary-format istructio back ito assembler laguage (problem 5). Name: Studet ID Number: Problem Score 1 (15) 2 (10) 3 (15) 4 (20) 5 (15) 6 (10) 7 (15) Total (100)

2 EE Uiversity of Miesota [1] (15 poits) Iteger Multiply Recall the hardware multiplicatio algorithm discussed i sectio 3.3. Show how this algorithm works for the followig iputs: multiplier = 0111 ad the multiplicad = Iteratio Step Multiplier Multiplicad Product 0 1a: Prod=Prod + Mcad : Shift left Multiplicad 3: Shift right Multiplier

3 EE Uiversity of Miesota [2] (10 poits) Little- ad big-edia byte orderigs. Assume that a MIPS processor has register $s0 set to the followig hexadecimal value: $s0 = AABBCCDD (a) (5 poits) The MIPS stadard byte-orderig is big-edia. If we store the 32-bit word i register $s0 i memory via the followig istructio: sw $s0, 0($zero) show how the bytes are stored i memory (big-edia): Memory Address 3 Memory Address 2 Memory Address 1 Memory Address 0 DD CC BB AA (b) (5 poits) Now, assume that MIPS uses little-edia byte-orderig istead. If we store the 32-bit word i register $s0 i memory via the followig istructio: sw $s0, 0($zero) show how the bytes are stored i memory (little-edia): Memory Address 3 Memory Address 2 Memory Address 1 Memory Address 0 AA BB CC DD

4 EE Uiversity of Miesota [3] (15 poits) MIPS istructios to implemet pseudo-code. For each of the followig pseudo-code istructios, show the shortest sequece of MIPS istructios that will implemet the pseudo-code: (a) move $s1, $s2 # move the value i register $s2 to register $s1 addi $s1, $s2, 0 or ori $s1, $s2, 0 or add $s1, $s2, $zero etc. (b) blt $s1, $s2, L2 # brach to L2 if $s1 < $s2 slt $at, $s1, $s2 be $at, $zero, $L2 (c) eg $s1, $s2 # egate (take 2s complemet of) value i register $s2 # ad place result i register $s1 subu $s1, $zero, $s2

5 EE Uiversity of Miesota [4] (20 poits) Covert the followig C statemet ito MIPS code. Assume that the variables f, g, h, i, ad j are assiged to registers $s0, $s1, $s2, $s3, $s4, respectively. Assume that arrays A ad B are iteger 32-bit iteger arrays, ad that the addresses of the arrays A ad B are i registers $s6 ad $s7, respectively. Cout the umber of istructios ad registers required by your code ad iclude those umbers i your aswer, e.g., my code for this problem uses 7 registers ad 13 istructios. Please ote: you may overwrite the registers for g, h, i, j i your code. f = (g + h) (i + j) + (A[6] + B[10]) addu $s0, $s1, $s2 # f=g+h addu $t0, $s3, $s4 # t0=i+j subu $s0, $s0, $t0 # f=f-t0 lw $t0, 24($s6) # t0=a[6] lw $t1, 40($s7) # t1=b[10] addu $t0, $t0, t1 # t0=t0+t1 addu $s0, $s0, $t0 # f=f+t0 This code uses 7 istructios, 9 registers

6 EE Uiversity of Miesota [5] (15 poits) The followig table cotais bits that represet the opcode of a istructio. You will eed to traslate these etries ito assembly code ad determie what format of MIPS istructios the bits represet. Word Word (a) ( 5 poits) What istructios do the biary umbers above represet? Provide a aswer for both Word 1 ad Word 2. Word 1: lw $t4, 12($t0) Word 2:ad $s1, $s2, $s3 (b) (5 poits) What type (I-type, R-type) of MIPS istructio do the biary etries above represet? Provide a aswer for both Word 1 ad Word 2. Word 1: I-type Word 2: R-type (c) (5 poits) If the etries i the table were data, bits, what umber would they represet i hexadecimal? Provide a aswer for both Word 1 ad Word 2. Word 1: 8D0C000C Word 2:

7 EE Uiversity of Miesota [6] (10 poits) istructio time calculatio Cosider three differet processors P1, P2, ad P3 executig the same istructio set with the clock rates ad CPIs give i the followig table: Processor Clock Rate CPI P1 5 GHz 4.0 P2 1 GHz 2.0 P3 10 GHz 5.0 (a) Which processor has the highest performace? Istructios per secod: P1: 5GHz/4 = 1.25 * 10 9 P2: 1GHz/2 = 0.5 * 10 9 P3: 10GHz/5 = 2.0 * 10 9 (b) If processor P2 executes a program i 10 secods, fid the umber of cycles ad umber of istructios. 10 sec * 1GHz = 10 * 10 9 cycles 10 sec * (0.5 * 109) ist/sec = 5 * 10 9 istructios

8 EE Uiversity of Miesota [7] (15 poits) Amdahl s Law. Develop a expressio for Amdahl s Law for a parallel computer that shows the attaiable speedup (To/T) assumig: (1) the performace improvemet for the parallel portio of a program is (assumes parallel computers workig o the problem); (2) x% of the program is serial ad caot be parallelized. Recall from homework #1 the followig equatio for Amdahl s Law: To = old executio time (ruig serial program o serial machie) T = ew executio time (ruig parallel versio of origial program o a parallel machie, assume there are o ew istructios for parallel operatio -- a idealizatio) = parallel speedup x = percet of the program that is iheretly serial ad caot ru i parallel T = To*(1-x)/ + To*x (a) Develop the expressio for speedup To/T where the right-had side of the equatio icludes oly the variables x ad : 1 x T = To + To x 1 x T = To x + To 1 = T 1 x x + (b) Show the form for the equatio whe becomes very large ( --> ifiity). How does the serial portio of a program limit the ultimately achievable speedup (To/T) o a ifiitely parallel machie? What is the achievable speedup for extremely large whe x = 0.5? Whe x = 0.01? T T = as x o 1 To if x=0.5, = 2 T To if x=0.01, = 100 T