ENSC E-123: HW D3: Counter Applications; Counter in Verilog

Transcription

1 HW D3; Counter Applications 1 ENSC E-123: HW D3: Counter Applications; Counter in Verilog REV 0 1 ; February 12, 2015 Contents 1 Counter Applications: Sync vs Async Function (5 points) Crummy: asyncclear(2points) Good: fully synchronous divide-by-eleven (3 points, total) Timing Diagram of Synchronous vs Asynchronous Schemes (3 points) 4 3 Modify a Counter, using Verilog (5 points) Draw your design (1 point) Try our design (2 points) Modify the Counter (2 points) A Sequential Digital Lock (5 pts) SequentialDigital Lock: draw it Total points: 18 pts Due Thursday, Feb 19, Revisions: cut Veri version of sequential lock (2/14); add state machine (lock) (2/13); add Verilog counter problem (2/08); merges counter problems from spring 04 XB wi fall 04 P123.

2 HW D3; Counter Applications 2 1 Counter Applications: Sync vs Async Function (5 points) Use a 74HC161, a 4-bit binary up counter with synchronous load, asynchronous clear, to make a divide-by-eleven counter in several ways: Note: CY is high if Count = 15, and if EN T is asserted; CY is low otherwise; the counter simply holds its present state if EN T is not asserted; Synchronous Load : Data (at the 4 D inputs) is loaded into the counter on the next rising edge of the clock if LD* is low (with setup time as given below) 1.1 Crummy: async clear (2 points) Show how to use the asynchronous clear to make a crummy divide-by-eleven counter: By the way, what s so crummy about this design?

3 HW D3; Counter Applications Good: fully synchronous divide-by-eleven (3 points, total) 1- Let the counter run up from state zero (1 point) 2- Use any states you like, taking advantage of the CarryOut function (2 points)

4 HW D3; Counter Applications 4 2 Timing Diagram of Synchronous vs Asynchronous Schemes (3 points) In the preceding question, you used both an asynchronous (crummy) method, and a fully-synchronous (classy) method. Your counters, in two cases, ran from zero up, and were to divide by 11. Use the timing diagrams below to show how the sync version is better than the async. Let your timing diagrams begin near the end of the cycle: at count 9, and show what happens in the next 4 clock periods.

5 HW D3; Counter Applications 5 3 Modify a Counter, using Verilog (5 points) Here, we d like to let you sample some of the fun of using Verilog, without the annoyances. We ve provided a very simple synchronous counter design no carry-in or carry-out; just 2 bits; an asynchronous reset. You know how to design such a thing. 3.1 Draw your design (1 point) Draw this 2-bit counter, please: Now draw a 3-bit version of such a counter: 3.2 Try our design (2 points) Load the project two bit simplest ctr.ise after unzipping it (download from website). Compile and simulate; confirm that it works OK on your machine. A print of the design and testbench files is just below. Now look at the Technology Schematic under Synthesize: double click, and you ll see a box. Click on that box to push into the schematic, seeing what s inside. You can push deeper. If push into doesn t seem to be available, try highlighting some element of the schematic that is shown. Eventually, you ll have pushed as deep as you can go, where you should find an XOR function, done with OR s and an AND. Please print the schematic (not the lowest level), and draw arrows and legends to show how this schematic relates to your own (we hope they are very similar!). 3.3 Modify the Counter (2 points) Modify this counter so as to let it count UP or DOWN. Add one more input, named UP, which makes this selection. You can do the job, then, by adding one more IF condition. Please print out the source file and the simulation result (you ll need to try asserting UP, clocking a few times, then disasserting UP, clocking a few times, in the testbench; so, you ll add a few lines to the...tb.vfile).

6 HW D3; Counter Applications 6 Simplest Counter Verilog Design Company: Engineer: Create Date: 21:28:11 02/20/2008 Design Name: Module Name: two_bit_simplest_ctr Project Name: Target Devices: Tool versions: Description: Dependencies: Revision: Revision File Created Additional Comments: module two_bit_simplest_ctr(clk, reset_bar, count); list the signals input clk;...say if they re in or out input reset_bar; output [1:0] count; this is a 2-bit variable wire clk, reset_bar; jargon used for inputs reg count;...and outputs when using "always@(..." form always@(posedge clk,negedge reset_bar) despite the name, reset_bar is not edge-sensitive if ( reset_bar) level-sensitive count <= 2 b00; else count <= count +1; clock really IS edge-sensitive endmodule And the testbench for SIMPLEST COUNTER: timescale 1ns / 1ps Company: Engineer: Create Date: 21:46:32 02/20/2008 Design Name: two_bit_simplest_ctr Module Name: C:/Documents and Settings/hayes/Desktop/xilinx_files/TOM/two_bit_simplest_ctr/two_bit_simplest_ctr_ Project Name: two_bit_simplest_ctr Target Device: Tool versions: Description: Verilog Test Fixture created by ISE for module: two_bit_simplest_ctr Dependencies: Revision: Revision File Created Additional Comments: module two_bit_simplest_ctr_tb_v;

7 HW D3; Counter Applications 7 Inputs reg clk; reg reset_bar; Outputs wire [1:0] count; Instantiate the Unit Under Test (UUT) two_bit_simplest_ctr uut (.clk(clk),.reset_bar(reset_bar),.count(count) ); initial $monitor ("clk = %b, reset_bar = %b, count=%b", clk, reset_bar, count); initial begin Initialize Inputs #10 clk = 0; reset_bar = 0; Wait 100 ns for global reset to finish #100; Add stimulus here #10 reset_bar = 1; #10 reset_bar = 0; test the reset #10 reset_bar = 1; forever repetitions that don t go on forever because of end "#150 $stop;" just below initial begin #150 $stop; this terminates simulation after this many time units end end endmodule Now the testbench for UP/DOWN COUNTER (your design): {\scriptsize \begin{verbatim} timescale 1ns / 1ps Company: Engineer: Create Date: 21:46:32 02/20/2008 Design Name: two_bit_up_dn_ctr Module Name: C:/Documents and Settings/hayes/Desktop/xilinx_files/TOM/two_bit_simplest_ctr/two_bit_simplest_ctr_ Project Name: two_bit_up_dn_ctr Target Device: Tool versions: Description: Verilog Test Fixture created by ISE for module: two_bit_simplest_ctr Dependencies:

8 HW D3; Counter Applications 8 Revision: Revision File Created Additional Comments: module two_bit_up_dn_ctr_tb_v; Inputs reg clk; reg up; reg reset_bar; Outputs wire [1:0] count; Instantiate the Unit Under Test (UUT) two_bit_simplest_ctr uut (.clk(clk),.up(up),.reset_bar(reset_bar),.count(count) ); initial $monitor ("clk = %b, up = %b, reset_bar = %b, count=%b", clk, up, reset_bar, count); initial begin Initialize Inputs #10 clk = 0; up = 1; reset_bar = 1; Wait 100 ns for global reset to finish #100; skip this delay, to keep display simple Add stimulus here #10 reset_bar = 0; test the reset #10 reset_bar = 1; repeat (8) gives us four rising clock edges (UP) #10 up = 0; now count down repeat (6) end endmodule

9 HW D3; Counter Applications 9 4 A Sequential Digital Lock (5 pts) Later we will want you to get a sense of one of Verilog s strengths: it makes designing a state machine pretty straightforward. Before we ask you to do the job with Verilog, we ll ask for a different sort of implementation, done with a shift-register and gates. We may return to this exercise in Verilog, in later HW. We ll try to describe how the circuit should behave, first. Theblockdiagramforthe...drawit sub-question (fig.1), may help you see what we re getting at. Here s the scheme: the lock faces the user with three switches: a toggle switch lets the user choose a HI or LO input LEVEL; a pushbutton switch,, CLOCKIT, lets the user clock in that LEVEL; a second pushbutton switch, TRY, lets the user say that she thinks she has put in a valid code; the machine is to respond as follows: each time the user pushes CLOCKIT the machine takes in the current LEVEL; if the user presses TRY, holding it pressed, and then presses CLOCKIT, the machine judges whether the sequence of bits put in matches the lock s code if the sequence does match, the circuit s output bit, UNLOCK, opens the lock; if the sequence does not match, the machine is reset to its initial state (and, of course, the lock is not opened). 4.1 Sequential Digital Lock: draw it Here is a block diagram/sketch of the circuit we d like you to detail: Figure 1: Sequence Detect Lock: rough sketch Please detail all the circuits, including how you would generate the signals CLOCKIT and TRY. The secret code is determined by a 3-position DIP switch, whose output is fed to the COMPARE circuit (we do this so we can change the key code).

10 HW D3; Counter Applications 10 This page for your circuitry: (hwd3 feb15xb.tex; February 12, 2015