Example of Digital System Design
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1 Example of Digital ystem Design The integrated circuit design process ystem Level Register Level Gate Level Fault imulation (gate level fault model) Fault imulation (transistor level fault model) Transistor Level Requirements & pecifications rchitectural Design Functional Design Logic Design Physical Design Fabrication Process Wafer Level Testing aw part Packaging & Testing ehavioral imulation (VHDL) Functional imulation (RTL VHDL or Verilog) Logic imulation (UIM) Circuit imulation (PPICE) Note all the simulation (design verification) - helps to ensure the design works and assists in debugging design errors In order to simulate a circuit, we must describe it in a manner that can be interpreted and understood by the simulator. C. E. troud ELEC
2 Design Capture with Hardware Description Languages Netlist Connections via signal name (like L) chematic Connections either explicit or via signal name Produces a netlist for simulation Higher level language (VHDL or Verilog) ynthesis to gate level netlist ll of these design descriptions can go to simulation for design verification C. E. troud ELEC
3 Key Ingredients of Hareware Description Languages (HDLs) Circuit statement: Circuit name Inputs Outputs Component statements: Component type Component instantiation Inputs signals Output signals G1 N G4 ckt: MUX in: out: ; not: G1 in: out: N ; and: in: N out: ; and: in: out: ; or: G4 in: out: ; C. E. troud ELEC
4 Hierarchical Design Hierarchical design saves time & design errors Once a subcircuit has been simulated & is known to work Most HDLs support hierarchical design MUX C. E. troud ELEC In0 In1 In2 In3 0 1 Out
5 Key Ingredients of HDLs Hierarchy (subcircuits) Connection via signal names (or netnames) Keyword notation Positional notation us notation C. E. troud ELEC G1 N subckt: MUX in: out: ; not: G1 in: out: N ; and: in: N out: ; and: in: out: ; or: G4 in: out: ; ckt: MUX4 in: In[0:3] [0:1]out: Out ; MUX: M1 in: In0 In1 0 out: M1 ; MUX: M2 in: In2 In3 0 out: M2 ; MUX: M3 in: M1 M2 1 out: Out ; G4
6 Hierarchical Design Hierarchical design supported in most HDLs VHDL, Verilog, L Netlist subckt: MUX in: out: ; not: G1 in: out: N ; and: in: N out: ; and: in: out: ; or: G4 in: out: ; ckt: MUX4 in: In[0:3] [0:1] out: ut ; MUX: M1 in: In0 In1 0 out: M1 ; MUX: M2 in: In2 In3 0 out: M2 ; MUX: M3 in: M1 M2 1 out: Out ; In0 In1 In2 In3 M1 M1 M3 M2 M2 0 1 ut C. E. troud ELEC
7 Design Verification chematic (or logic diagram) N G1 G4 Netlist ckt: MUX in: out: ; not: G1 in: out: N ; and: in: N out: ; and: in: out: ; or: G4 in: out: ; Logic imulation Netlist Logic imulator imulation Results timuli C. E. troud ELEC
8 Design Verification Logic simulation results used To verify proper operation of design To find and fix problems (errors) in design akadebugging Input timuli (or vectors) # ; imulation Results # ; compare simulation results to truth table C. E. troud ELEC
9 Key Ingredients of Logic Design Logic simulation results used To verify proper operation of design (design verification) To find and fix problems (errors) in design (aka debugging) Input timuli (or vectors) # ; imulation Results # ; C. E. troud ELEC
10 Design Capture Input chematic diagram G1 N Netlist ckt: MUX in: out: ; not: G1 in: out: N ; and: in: N out: ; and: in: out: ; or: G4 in: out: ; imulation G4 NOT ND ND C. E. troud ELEC Computer Emulation Data structures to hold logic values Pointers to source logic values OR logical operations performed by computer
11 Types of imulators Compiled imulator (UIM) imulation continues until circuit is stable No changing logic values within circuit ka: unit delay or logic simulator ll gates in circuit have a finite unit delay Good for initial design verification hort simulation times Event-Driven imulator imulation events scheduled in time Circuit may not be stable when input changes ka: timing simulator Gates have real delays base on intrinsic & extrinsic factors More accurate for real circuits longer simulation times and more computer intensive C. E. troud ELEC
12 Other CD Tools in Logic Design udits for potential design problems uch as no-connects or multiple gates driving same net Usually part of another tool (schematic capture or simulator) Logic minimization tools Handles combinational logic circuits too big for K-maps Timing analysis Finds and reports worst case timing delay path Like P del but uses actual timing parameters per gate C. E. troud ELEC
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EE 4755 Digital Design Using Hardware Description Languages Basic Information URL: http://www.ece.lsu.edu/v Offered by: David M. Koppelman, Room 345 ERAD Building 578-5482. koppel@ece.lsu.edu, http://www.ece.lsu.edu/koppel/koppel.html