Agenda. Presentation Team: Agenda: Pascal Bolzhauser, Key Developer, Lothar Linhard, VP Engineering,

Transcription

1 Welcome JAN 2009

2 Agenda Presentation Team: Pascal Bolzhauser, Key Developer, Lothar Linhard, VP Engineering, Agenda: Company Overview Products: GateVision RTLVision SpiceVision Questions and Answers 2

3 Company Overview Founded: 1990 Privately held. Location: Freiburg, Gemany (plus Sales REPs) One Focus: Automatic Schematic Generation combined with Interactive Viewing (graphical debugging). Provide: OEM-component (Nlview) and end-user-tools (*Vision) 3

4 Product Overview Customizable Debugging tools for IC/SoC/FPGA designers: Concept Engineering s customizable Debugging tools provide electronic design engineers with the ability to understand, optimize and debug their gate-level designs (GateVision), RTL-level design (RTLvision) and transistor-level designs (SpiceVision) - to get their products faster to market with a higher degree of confidence. 4

5 Product Overview Mixed Level Debugging tool for IC/SoC/FPGA designers: SGvision is a merger of SpiceVision and GateVision. It helps to analyze mixed level descriptions, both, block level structures described in Verilog and lower level structures described in SPICE, can be debugged in a single tool. 5

6 *VISION Product Highlights Highlights: Easy-to-use, Simple Slim Tool - Quick startup Extendable: > Tcl API includes full db access (Userware) > Gui API (Tcl/Tk) GUI: Object Drag & Drop Support for big designs (64 bit) Pre-compiled designs (.zdb) Support for command line compilation Very open environment One GUI, one API, all design levels Customization: For Example: Users can write own electrical rule checkers (ERC) and statistical checkers, and display results. For Example: User can write parser for report files (e.g. Primetime) and display results. 6

7 Multi-View GUI Hierarchy Tree Explore Neighbourhood Schematic e.g. trace a signal Incremental Schematic Display Result of autom. cone extraction, userware. Schematic Fragment increases readability. Cone 7

8 Multi-View GUI Schematic Search Results Memory Cross Probing Source Code Console 8

9 Fit in typical Design Flows Library Design & Optimization Product Spec RVLvision reads SystemVerilog, Verilog and VHDL. RTL-Simulation & Functional Verification Synthesis Static Timing Analysis & Gate-level Simulation SpiceVision reads Spice (different dialects). Floorplan & Partition Place & Route Physical Verification GateVision reads Verilog and EDIF 200 netlist. Tape-out 9

10 GateVision in typical Design Flows Analyze/Understand timing errors ECO changes. Library Design & Optimization Product Spec RTL-Simulation & Functional Verification Synthesis Static Timing Analysis & Gate-level Simulation Floorplan & Partition Full Chip Netlist Analyze output of Synthesis Test Insertion Clock Tree Insertion FPGA Partitioning Place & Route Physical Verification GateVision reads Verilog and EDIF 200 netlist. Tape-out 10

11 GateVision Interfaces Input files: Verilog Netlist EDIF 200 Netlist SDF PrimeTime Report API Primetime Userware Output files: Print: PS, EDIF, GIF Verilog Netlist (fragment) Bookmark Files (fragment) Customer File User Defined Functions Customer File 11

12 GateVision - DEMO Common GUI features Hierarchy Tree Mouse Strokes, etc (basic GUI use) Cross-probing between views (drag&drop) Highlight objects Trace a signal path in Cone window Automatic Path/Cone extraction Display Primetime report Incremental Schematic Save Fragment as Verilog netlist Pascal 12

13 RTLVision in typical Design Flows Library Design & Optimization Product Spec RTL-Simulation & Functional Verification Understand 3 rd party IP blocks RTL code (fragments) from other teams RVLvision reads SystemVerilog, Verilog and VHDL. Analyze output of tools that automatically change/create RTL code: Test Insertion Power Optimization, Synthesis Static Timing Analysis & Gate-level Simulation Floorplan & Partition Place & Route Physical Verification Tape-out 13

14 RTLVision Interfaces Clock Tree Analysis Clock Domain Analysis Verific Parser Input files: Verilog RTL SystemVerilog VHDL Output files: Print: PS, EDIF, GIF Verilog Netlist (cone) Bookmark Files (cone) SDF Customer File User Defined Functions Customer File 14

15 RTLvision - DEMO Trace a signal Source code cross-probe Automatic Path/Cone extraction ClockTree Analyzer 'multidriver' Userware example Pascal 15

16 SpiceVision in typical Design Flows Helps to optimize library cells for speed and power. Library Design & Optimization Understand function of foreign cells and IP blocks. Product Spec RTL-Simulation & Functional Verification Synthesis Static Timing Analysis & Gate-level Simulation Floorplan & Partition Place & Route SpiceVision reads Spice (different dialects). Understand output of LVS runs. Analyze extracted Spice netlists. Parasitics. Physical Verification Tape-out 16

17 SpiceVision Interfaces Parameter Editing SPICE Reader Input files: Output files: H Spice P Spice Spice 2 Spice 3 CDL Calibre DSPF Customer File Bring circuit (fragment) back to your standard User Definedenvironment Functions Print: Spice Netlist PS, EDIF, (new GIF param) Bookmark Spice Netlist Files (cone) (cone) Cadence Skill Export to Cadence Virtuoso: Customer File 17

18 SpiceVision Example Example: LM111 LM111 comparator simulation model model (Source: TI) TI) Cross probing: Schematic/SPICE 18

19 SpiceVision Example Example: EL7212 EL7212 High High Speed Speed Driver Driver (Source: Intersil) Intersil) Compare: Spice Spice Simulation Model Model and and Data Data Sheet Sheet 19

20 SpiceVision Exploring Parasitics Gate-level netlist (Verilog) and corresponding DSPF netlist (parasitics) 20

21 SpiceVision - DEMO Transistor Circuit Examples (nand, dff, mux) Analyze Spice netlist and identify the function Extracted netlist example Trace a signal in the Cone window Show Userware examples (ERC) Symbol shapes for sub-circuits (gates) Advanced Cone features (fold/unfold, inflate hierarchy block, hide pins) Display Pathmill report Display DSPF & Verilog - SGVision Pascal 21

22 *VISION - Key Benefits Visualization Tools with builtin debugging functions Easy to use: Intuitive GUI provide different views to YOUR design data and easy cross-probing between them (drag & drop). Built-in debug support like path extraction or clock tree extraction Extend/Customize: Very open to extension and customer specific features and provide easy integration into existing design flows. Performance & Capacity: Lightweight tool provides high capacity and CPU performance (64 bit db and pre-compile features). 22

23 Contact us! Concept Engineering GmbH Bötzinger Str. 29 D Freiburg, Germany Phone: Fax: