ELEG 5173L Digital Signal Processing Introduction to TMS320C6713 DSK

Transcription

1 Departmet of Electrical Egieerig Uiversity of Arasas ELEG 5173L Digital Sigal Processig Itroductio to TMS320C6713 DSK Dr. Jigia Wu

2 ANALOG V.S DIGITAL 2 Aalog sigal processig ASP Aalog sigal processig is achieved by usig aalog compoets such as: Resistor, capacitor, iductor Sesitive to iheret toleraces, temperature, voltage chages ad mechaical vibratios They ca dramatically affect the effectiveess of the aalogue circuitry Digital sigal processig DSP High precisio High tolerace to oise Short developmet time High fleibility Low power cosumptio Digital sigal processig techiques are ow so powerful that sometimes it is etremely difficult, if ot impossible, for aalogue sigal processig to achieve similar performace.

3 DSP 3 Digital Sigal Processor DSP A digital sigal processor is a specialized microprocessor with a architecture optimized for the fast operatioal eeds of digital sigal processig It is a special type of microprocessor Have istructios desiged specifically for digital sigal processig Use a DSP whe the followig are required: Cost savig. Smaller size. Low power cosumptio. Processig of may high frequecy sigals i real-time. Use a geeral purpose microprocessor e.g. Itel Core 2 Duo whe the followig are required: Large memory. Advaced operatig systems.

4 DSP DSP The ey operatio i digital sigal processig is sum of products SOP or multiply ad accumulatio MAC 4 Algorithm Equatio Fiite Impulse Respose Filter M a y 0 Ifiite Impulse Respose Filter N M y b a y 1 0 Covolutio N h y 0 Discrete Fourier Trasform 1 0 ] / 2 ep[ N N j X Discrete Cosie Trasform cos. N u N f u c u F

5 DSP 5 DSP are optimized for MAC operatios Multiplicatio ad additio are doe i hardware ad i oe cycle. Eample: 4-bit multiply usiged. Hardware Microcode Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 DSP geeral purpose microprocessor

6 TEXAS INSTRUMENTS TMS320 FAMILY 6 C2000 C5000 C6000 Lowest Cost Cotrol Systems Motor Cotrol Storage Digital Ctrl Systems Efficiecy Best MIPS per Watt / Dollar / Size Wireless phoes Iteret audio players Digital still cameras Modems Telephoy VoIP Performace & Best Ease-of-Use Multi Chael ad Multi Fuctio App's Comm Ifrastructure Wireless Base-statios DSL Imagig Multi-media Servers Video

7 TMS320C TMS320C6713 Very-log-istructio-word VLIW architecture Suited for umerically itesive algorithms. 8 istructios ca be fetched per cloc cycle E.g. cloc rate 225 MHz, cloc period = 1/225 MHz = 4.44 s 8 istructios ca be fetched every 4.44 s. 264 KB iteral memory. 6 Arithmetic ad logic uits ALUs 2 multiplier uits 32 bit address bus up to 4 GB memory 2 sets of 32-bit registers Capable of both fied poit ad floatig poit processig.

8 TMS320C6713 DSK 8 TMS320C6713 DSK a low-cost developmet platform desiged to speed the developmet of applicatios based o TI s TMS320C6713 DSP 512K Flash ad 16MB SDRAM DSP operatig at 225 MHz A AIC32 stereo codec CPLD: Comple Programmable Logic Device McBSP: Multi-chael buffered serial ports

9 DEVELOPMENT ENVIROMENT 9 Gettig started: 1. lauch widows XP mode Start Computer widows C: VMz Code_Composer_p widows XP Mode 2. plug the DSK to PC through USB port, power DSK o.

10 DEVELOPMENT ENVIROMENT cot d 10 Gettig started: 3. i Widows XP mode, USB TMS320C6713DSK Attach 4. o Widows XP mode destop, lauch 6713DSK CCStudio V If a Waitig for USB eumeratio dialog bo show up, repeat step I CC Studio 3.1, Debug Coect. If successful, the left lower corer of CC Studio 3.1 should be chaged from to If ay of the above step does ot wor, try to uplug DSK, shut dow Widows XP mode, ad try steps 1 6 agai.

11 EXAMPLE 11 si8_led.c

12 EXAMPLE si8_buf.c AIC23 will geerate a iterrupt at every sample istat fs = 8KHz: 8,000 iterrupts will be geerated by the AIC23 Every time a iterrupt is geerated, c_it11 will be eecuted. 12