Digital Design using HDLs EE 4755 Final Examination

Transcription

1 Nme Solution Digitl Design using HDLs EE 4755 Finl Exmintion Thursdy, 8 Decemer 6 :3-4:3 CST Alis The Hottest Plce in Hell Prolem Prolem Prolem 3 Prolem 4 Prolem 5 Prolem 6 Exm Totl (3 pts) ( pts) (5 pts) (5 pts) ( pts) ( pts) ( pts) Good Luck!

2 Prolem : [3 pts] The digrm nd Verilog code elo sho incomplete versions of module pro_seq. This module is to operte something like mg_seq from Homeork 6. When strt is t positive clock edge the module ill set redy to nd strt computing v*v v*v v*v, here v nd v re ech IEEE 754 FP single vlues. The module ill set redy to t the first positive edge fter the result is redy. Complete the Verilog code so tht the module orks s indicted nd is consistent ith the digrm. It is oky to chnge declrtions from, sy, logic to uire. But the synthesized hrdre cnnot chnge ht is lredy on the digrm, for exmple, don t remove register such s c nd don t insert ny ne registers in existing ires, such s those eteen the multiplier inputs nd the multiplexors. Don t modify this digrm, rite Verilog code. strt pro_seq redy v m c CW_fp_dd result v 3' 3' clk 'd c Don t modify this digrm, rite Verilog code.

3 Prolem, continued: Solution on this pge. Complete Verilog so tht module computes v*v v*v v*v. Synthesizedhrdremusteconsistentithdigrm, espelly synthesized registers. Note tht redy must come from register. Don t skip the esy prt: connections to dder. strt v v clk Don t modify, Verilog only. pro_seq 3' m 'd c c CW_fp_dd 3' redy result module pro_seq( output uire [3:] result, output logic redy, input uire [3:] v, v, input uire strt, clk); uire [7:] mul_s, dd_s; uire [3:] mul_, mul_; uire [3:] dd_, dd_; uire [3:] prod, ; logic [3:] c, c; logic [:] step; loclprm int lst_step = 4; // SOLUTION. posedge clk ) if ( strt ) step = ; else if ( step lst_step ) step = step ; m(.(mul_),.(mul_),.(),.z(prod),.sttus(mul_s)); CW_fp_dd (.(dd_),.(dd_),.(),.z(),.sttus(dd_s)); // ssign redy = step == lst_step; // SOLUTION: Remove this line. // SOLUTION (reminder of module is solution) ssign mul_ = step? v : v; // Connect FP multiplier ports.. ssign mul_ = step ==? v : v; //.. to pproprite vlues. ssign dd_ = c, dd_ = c; // Connect FP dder input ports. posedge clk ) egin c = prod; // Assign registers c, c, nd redy. // Alys rite c. cse ( step ) // Set c sed on the step vlue.. : c = ; //.. *efore* the positive clk edge., : c = ; endcse if ( strt ) redy = ; // Reset redy *efore* step.. else if ( step == lst_step- ) redy = ; //.. nd set redy hen ill e done. end ssign result = ; // Connect FP dder output to this module s output. endmodule 3

4 To understnd ho the solution orks refer to the timing digrm elo. Note tht the vlue of step in the second lys ff is efore it is incremented. strt pro_seq redy v m c CW_fp_dd result v 3' 3' clk 'd c clk strt step mul_ v v mul_ v v Mux dely. prod c c redy Mult dely. v² vv v² v² vv v² v² v² vv v² vv v² v² vv v² 4

5 Prolem : [ pts] Anlyze the timing of the to similr modules on the next pge using the timing model used in clss, s requested in the suprolems. Ase tht ll dders re synthesized s ripple connection of inry full dders nd tht the comprison units re lso sed on ripple hrdre. () Before nlyzing the modules, sho the dely of ech of the components listed elo using the simple model given in clss. For this prt se tht ll inputs re ville t t =. In the simple timing model the dely of n n-input AND nd OR gte is lgn units, hich orks out to for -input gtes. For lrger gtes the dely is ht ould e otined y constructing reduction tree of -input gtes. NOT gtes hve dely of zero. Other comintionl logic is sed on the dely of n implementtion using AND, OR, nd NOT gtes. For exmple, the dely of -input XOR gte is. 5

6 Dely for BFA is: The dely (of f-unopt) is 4 units for the nd 3 units for co. Explin or sho digrm. Short Anser: The dely is sed on the f-unopt BFA implementtion elo. The loer digrm shos the timing nlysis. Long Anser: Appering elo re to implementtions of inry full dder, shon ith nd ithout timing nlysis. In the first, f-unopt, seprte logic is used to generte the nd crry out signls. In the second, f-fst, n XOR gte is shred y the nd crry out logic, oth redung cost nd redung the criticl pth in ripple dder. The lue lels sho the gte delys, rcled numers sho the time tht signl is ville. The purple signls sho the timing underthesptionthtllsignlsrrivetmoduleinputst = ndthegreensignlsshothetimingunderthesptiontht the crry in signl rrives t t = ut tht the nd signls rrive t t =. The rtionle for the green signls sption is tht hen BFA is used s prt of ripple dder the crry in signl for ll ut the lest-significnt it BFA ill rrive lter thn the nd inputs. Note tht even ith the nd signls rriving erly the dely for co in BFA-unopt ould still e 3. In mry: For BFA-unopt, t t = 4 nd crry out t t = 3. For BFA-fst ith ll signls rriving t t =, the is ville t t = 4 nd crry out t t = 4. With erly rrivl, the crry out is ville t t =. BFA-unopt BF BFA-unopt 4 3 Crry-in rrives >= units lter. E.g., in BFA units fter LSB. All signls rrive t sme time. E.g., BFA t LSB BF

7 Dely for -it dder is: Using BFA-unopt the dely for > is 3 units for the crry out nd 3 units for the MSB of the. Explin or sho digrm. [] [] r ple_dder [] [] [-] [] [] [-] Bit -- LSB Bit Bit Bit - -- MSB BFA-unopt BFA-unopt BFA-unopt BFA-unopt 3(-) Dely for it - -- MSB Dely for it -- LSB 4 3- Short Anser: As shon in red in the digrm ove, the criticl pth psses from to co of the linerly-connected BFAs, so the totl dely is 3 using BFA-unopt or using BFA-fst. When BFA-unopt is used the co signl of the BFA for it i is ville t 3(i), here i = is the lest-significnt it. If the -it dder itself hs crry-out signl, the dely is 3 its, sed on the vilility of the crry out t it. If there is no crry out then the dely of the MSB is to units fter the rrivl of the crry in, so the totl dely is 3( ) = 3 units. Bit i =, the LSB, of the is redy t t = 4, it i of the is redy t 3i. When BFA-fst is used the co signl is ville t time 4 for the LSB, for it i it is ville t 4i. The is ville cycles fter the rrivl, so overll timing is 4( ) = hether or not crry out is used. Dely for -it (less thn) comprison unit is: Using sutrction, 3 units sed on BFA-unopt or units using BFA-fst. Explin or sho digrm. To compute use -it dder to compute, here nd re -it unsigned numers. (To perform sutrction the inputs re inverted nd the dder crry in is set to. This doesn t ffect cost or dely under the simple model since NOT gtes re free nd zero-dely.) If the crry out is zero then the difference is negtive nd so is true. Note tht logic tht is only used for computing is omitted. Using BFA-unopt the dely is 3, using BFA-fst the dely is. (In oth cses the cost is 5. In BFA-unopt oth XOR gtes re eliminted. In BFA-fst one XOR gte is eliminted nd the other is replced ith n OR gte.) Dely for -it, n-input multiplexor is: The dely is lg lgn lgn units. Explin or sho digrm. 7

8 s mux n, One decode AND per input (n totl). s[lg(n)-] s= s= lg lg n gte ANDs per input (n totl). OR gtes lg n (lg lg n) lg n x (n-) s=n- As shon in the illustrtion ove ech mux input hs n AND gte decoding the select signl (ith some inputs inverted sed on the mux input numer). The AND gte hs lgn inputs (hich is the numer of its in the select signl) nd so y the simple model hs dely of lg lg n units. (For revity the digrm omits the ceiling function.) The decoder nd input connect to nother AND gte, dding to the dely. Finlly, there is n n-input OR gte, contriuting nother lgn units of dely. 8

9 Prolem, continued: () Find the length of criticl pth in the to modules elo using the timings ove. Where pplicle mke the resonle sption tht ripple dder cn strt hen its loer its rrive, not hen ll its of its input re stle. [] [] [] [3] 3 36, 6 LSB Time 66 MSB Time 6, 98 98, [] [] [] [3] 4, 3 8, 34, Length of criticl pth for greedy fit in terms of. Sho ork for prtil credit. Short Anser: Using f-unopt the criticl pth length is units, see the digrm ove in hich the criticl pth is shon in red nd is leled ith timing long the criticl pth. Long Anser: The time for the comprison unit is 3 units. The time for n dder is 4 units to produce the LSB of the nd 3 for the complete, including the crry out. Note tht ecuse the comprison unit is implemented using the crry pth of n dder, it cn strt on the LSB s soon s it rrives (mening efore more significnt its rrive), nd it cn keep up ith the pce of ne input it eing redy every 3 time units fter the nd it. Signls rrive t the inputs to the[] dder t time 3 nd so the comprison gets its LSB t time 36, the next its t 37, 3, 33,... The comprison unit s output is redy t 3 63 = 6 6. Unfortuntely for the [] dder one of its inputs is the output of multiplexor, mening tht ll its rrive t the sme time nd so it cnnot strt erly. Length of criticl pth for fcfs fit in terms of. Sho ork for prtil credit. Short Anser: Using f-unopt the criticl pth length is 34 units, see the digrm ove in hich the criticl pth is shon in red nd is leled ith timing long the criticl pth. Green shos timing of non-criticl signls. Long Anser: Unlike greedy_fit the inputs to the dders in fcfc_fit re either module input or the output of nother dder. For this reson the totl dely through the 3 dders is Note tht 3 4 is the redy time of the LSB output of the lst (third) dder. 9

10 Prolem 3: [5 pts] Complete the Verilog code so tht it corresponds to the module shon. Complete module. The solution ppers elo. The module ould e slightly simpler if the if ( i > ) ere removed (mking the r=[i] unconditionl) nd r ere initilized to zero, ut tht ould not exctly correspond to the illustrtion. Full credit ould e given to either solution. [] [] [] [3] module fcfs_fit #( int nelts = 4, int = 6 ) ( output logic [-:], input uire [-:] [nelts], limit ); // SOLUTION lys_com egin end endmodule logic [-:] r; // Running. r = []; = ; for ( int i=; inelts; i ) egin if ( i > ) r = [i]; if ( r limit ) = r; end

11 Prolem 4: [5 pts] Appering to the right is fcfs_cfit, version of the fcfs_fit module in hich the input hs een chnged to prmeter, mening tht is n elortion-time constnt. Compute the cost of this module using the simple model used in clss nd ccounting for optimiztion sed on the constnt vlues. As in n erlier prolem, dders nd comprision units re ripple-style. 6h'4755 6h'47 6h'3755 6h'74 [] [] [] [3] n=4, =6, = Cost of the [] comprison unit. The cost is gtes. Explin. 6' [] [] B A p ' Optimiztion for [] it =. ' c c c pre [] B A p B A p Optimiztion for [] it =. Optimiztion for [] it =. c ' Becuse one input is constnt the 5 gtes per it using BFA-unopt is reduced to, either n AND gte or n OR gte. (If BFA-fst isusedthenthe4gtesperitislsoreducedto, eithernandoror.) Seethedigrmove. Thelestsignificnt it requires t most NOT gte, hich hs cost of zero. The totl cost is gtes. Cost of the [] dder. Explin. Since oth inputs re constnt the cost is zero.

12 Cost of the [] multiplexor. Explin. ' s m ' x ' s m x Optimiztion Pln Completed Optimiztion Sinceothinputsreconstntthecostiszero. Theoutput for it i 6 is either the constnt zero or, here n it is, is equl to the select signl. See the ottom ro of the -input mux optimiztion digrm to the right. ' s m x ' s m x Cost of the [] multiplexor. Explin. s m s m One input to the [] mux is constnt. Where the constnt input it is the logic is just n AND gte (top ro of digrm) here it is the logic is n AND nd n OR (middle ro of digrm). ' ' ' x ' ' x Totl cost.

13 Prolem 5: [ pts] Anser ech question elo. () A time slot in the Verilog event queue contins mny regions, mong them ctive, inctive, nd NBA. Explin ho n event gets put in ech region. (You cn use the next suprolem for exmples.) An event is put into the ctive region hen: Short Anser: When the ctive region is empty. Explntion: All events in the first non-empty region re copied into the ctive region. Of the regions tht hve een mentioned, the inctive region in the current time slot is checked first, folloed y the NBA region in the current time slot, folloed y the inctive region in the next scheduled time slot, etc. An event is put into the inctive region hen: Short Anser:... hen dely such s# is encountered in procedurl code nd hen vrile found in sensitivity list chnges. Explntion: Whendelysuchs#d(ford )isencounteredinprocedurlcodenreeeventillescheduledintheinctive region of time step td, here t is the current time slot. Note tht # is perfectly oky for those ho understnd SystemVerilog event timing. For exmple, in... =z; #; c=qr;... hen the # is reched ree event ill e put in the inctive region of the current time slot to ree execution t the c= sttement. If the dely hd een #3 then the ree event ould e put in the inctive region of time slot t3. For those events ith sensitivity list, such s lys com, continuous ssignments, nd module instntitions, events re scheduled hen vrile on the sensitivity list chnges. For exmple, consider lys com egin =xy;... When x chnges n event to execute the lys com lock ill e put in the inctive region. An event is put into the NBA region hen: Short Anser:... hen non-locking ssignment is executed. Explntion: For exmple, hen execution reches sttement like = the left-hnd side, in the exmple, ill immeditely e computed nd then n updte event ill e plced in the NBA region. The updte event crries the vlue of. Eventully the NBA region ill e copied to the ctive region nd the updte event ill e executed, cusing to chnge to the crried vlue. () In the code frgment elo sho the order in hich the sttements re executed fter the posedge clk. Identify sttement y the vlue tht is ssigned. The first to sttements executed re nd, tht s shon. (Since is nonlocking ssignment, the execution of only mens tht s computed, it doesn t men tht s chnged.) Complete the Order of sttements list. module regions; posedge clk ) egin = ; = ; end lys_com s = ; lys_com x = ; lys_com y = x 5; lys_com y = x 4; lys_com x = 3; endmodule Order of sttements:,, Short nser:,, s, x, y, s, x, y. 3

14 Prolem 6: [ pts] Appering elo is the pipelined mg module from Homeork 6. () Suppose it turns out tht the multiply () tkes tice s long s the dd (CW_fp_dd). Bsed on this fct, modify the pipeline to reduce cost, ut ithout ffecting clock frequency. Dr in your chnges, there s no need to rite Verilog. Also, comment on ltency nd throughput chnges. Modify for loer cost sed on fster dder. Solution ppers elo fter the unmodified module. The pipeline ltch eteen the to dders s removed. With this chnge the criticl pth length in the multiplier stge mtches the criticl pth in the dder stge. (Before this chnge the criticl pth length in ech of the dder stges s hlf the criticl pth in the multiplier stge.) Does the chnge help throughput? Does it help ltency? The chnge does not chnge throughput ecuse the clock frequency does not chnge. The module cn complete one clcultion per cycle ith or ithout the chnge. The chnge reduces (helps) ltency ecuse there is one less stge. pl_v[] pl_v[] pl_v[] 3' 3' 3' :m :m :m vsq[] vsq[] vsq[] mg pl_vsq[][] pl_vsq[][] pl_vsq[][] e CW_fp_dd 3' pl_sos[] pl_vsq[][] CW_fp_dd 3' pl_sos[3] mg pl_v[] 3' nd vsq[] mg pl_vsq[][] e CW_fp_dd Solution Pipeline removed. pl_v[] 3' nd vsq[] pl_vsq[][] 3' CW_fp_dd pl_sos[] mg pl_v[] 3' nd vsq[] pl_vsq[][] 3' 4

15 () Suppose tht the v input rrives very erly in the clock cycle. Bsed on this modify the pipeline to reduce cost. Modify for erly-rriving v. Short Anser: Solution ppers elo fter the unmodified module. Explntion: In this cse the pipeline ltch t the inputs s removed, sving the cost of the pipeline ltch. Since the inputs rrive erly there should e enough time to compute the products during the clock cycle in hich the inputs first rrive. The removed pipeline ltch ould e necessry if the inputs rrived lter in clock cycle, in tht cse the multipliction ould not strt until the next clock cycle. This modifiction does not chnge throughput ut does reduce ltency. pl_v[] pl_v[] pl_v[] 3' 3' 3' :m :m :m Stge vsq[] vsq[] vsq[] mg pl_vsq[][] pl_vsq[][] pl_vsq[][] e CW_fp_dd 3' pl_sos[] pl_vsq[][] CW_fp_dd 3' Stge Stge pl_sos[3] mg Solution mg e Pipeline ltch removed. 3' 3' nd nd vsq[] vsq[] pl_vsq[][] pl_vsq[][] CW_fp_dd 3' pl_sos[] CW_fp_dd pl_sos[3] mg 3' nd Stge vsq[] pl_vsq[][] pl_vsq[][] 3' Stge Stge 5