MCQ From PICT College of Engineering

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1 1. Intel s programmable device (8253) facilitates the generation of accurate time delays. a) counter b) timer c) both a & b d) none of these 2. The programmable timer device (8253) contains three independent bit counters. a) 8 b) 16 c) 20 d) The 8-bit data buffer interfaces internal circuit of 8253 to microprocessor systems bus. a) Unidirectional b) Single c) Bidirectional d) None of these 4. The three counters available in 8253 are independent of each other in operation, but they are to each other in organisation. a) Similar b) Opposite c) Identical d) Common 5. The speciality of the 8253 counters is that they can be easily read on line without disturbing the input to the counter. a) GATE b) CLK c) OUT

2 d) WR 6. The GATE signal is and should be for normal counting. a) Active Low, Low b) Normal, Normal c) Active High, High d) None of the Above 7. When GATE goes low counting is terminated and the current count is till the GATE again goes high. a) Disturb b) Latched c) Decrease d) Increase 8. If N is loaded as the count value, then, after N pulses, the output becomes low only for clock cycle. a) One b) Zero c) N d) (N-1) 9. In this mode, the 8253 can be used as a wave rate generator. a) Sine wave b) Cosine wave c) Square wave d) All of these e) 10. When count is N loaded in, then for half of the count, the output remains high and for remaining half it remain low. a) Odd b) Even

3 c) Even-even d) Odd-odd MCQ From PICT College of Engineering 11. If the count loaded is odd the first clock cycle pulse decrement by resulting in an even count value. a) 0 b) 1 c) -1 d) None of these 12. The processor 8085 had hardware interrupt pins. a) 4 b) 5 c) 6 d) The predecessor 8259 was designed to operate only with bit processors like a) 4 b) 8 c) 16 d) A modified version, was later introduced that is compatible with 8-bit as well as 16-bit. a) 8259

4 b) 8359 c) 8259A d) 8359A MCQ From PICT College of Engineering 15. stores all the interrupt requests in it in order to serve them one by one on the priority basis. a) IRR b) ISR c) IMR d) NMI 16. keeps a track of the requests being served. a) IRR b) ISR c) IMR d) NMI 17. stores the bits required to mask the interrupt input. a) IRR b) ISR c) IMR d) NMI 18. pin is an active low write enable input to 8259A a) WR b) WR c) Both a & b d) None of these 19. In Cascade Buffer/Comparator the same pins act as inputs when the 8259A is in a) Master

5 b) Slave c) Master-Slave d) All of these MCQ From PICT College of Engineering 20. goes high whenever a valid interrupt request is asserted. a) INT pin b) NMI pin c) IRR pin d) ISR pin 21. as inputs to accept interrupt requests to the CPU. a) IR₀-IR₇ b) CR₀-CR₇ c) DR₀-DR₇ d) TS₀-TS₇ 22. In an based system, A₁₅-A₈ of the interrupt vector address are the respective bits of ICW₂. a) 8008 b) 8080 c) 8085 d) In an 8086/88 based system of the interrupt vector address are inserted in place of T₇ -T₃ respectively. a) A₁₅-A₁₁ b) A₁₅-A₈ c) A₁₅-A₁₃ d) A₁₅-A₅ 24. Special fully nested mode is selected, if SFNM=.

6 a) 0 b) -1 c) 1 d) None 25. If AEOI=, the automatic end of interrupt mode is selected. a) 1 b) 0 c) -1 d) None 26. is the default mode of operation of 8259A. a) Real mode b) AEOI (automatic end of interrupt mode) c) EOI(end of interrupt mode) d) Fully Nested mode ANSWER: d 27. If bit LTIM of ICW₁=0, they are triggered a) Edge b) Level c) Both a & b d) None of these 28. The I/O section is enabled only if CS Is a) High b) Low c) Very high d) Very low

7 MCQ From PICT College of Engineering 29. RD /WR input pins enable the data buffers to receive or send data over the bus. a) Address b) Data c) Both a & b d) None of these 30. are used to scan the key board matrix and display digits. a) SL₀-SL₃ b) RL₀-RL₃ c) CL₀-CL₃ d) All of these 31. O/P pin is used to blank the display during digit switching or by a blanking command. a) BD b) BS c) BD d) BS 32. Scanned Keyboard Mode in encoded scan keyboard or in decode scan a Keyboard can be interfaced. a) 8*8,4*8 b) 4*8,8*8 c) 4*4,8*8 d) 8*4,4*8 33. Scanned Keyboard Special Error Mode is valid only under the key rollover Mode. a) 1 b) 50

8 c) N-1 d) N ANSWER: d 34. The 8-byte FIFO RAM now acts as bit memory matrix. a) 4*4 b) 4*8 c) 8*8 d) 8*4 35. In the left entry mode, the data is entered from the side of display unit. a) Left b) Right c) Front d) Back 36. In the right entry mode, the data is entered from the side of display unit. a) Left b) Right c) Front d) Back 37. In mode, data is transmitted only in one direction over a single communication channel. a) Simplex b) Duplex c) Half duplex d) Half simplex

9 38. input pins, together with RD and WR inputs, informs the 8251A that the word on the data bus is either a data or control word/status information. a) C/D-control Word/Data b) C/D -control Word/Data c) C /D-control Word d) C /D -control Word/Data 39. A high on RESET input forces the 8251A into an state a) Wait b) Ready c) Idle d) Hold 40. input controls the rate at which the character is to be transmitted. a) System clock b) Transmitter clock c) Bus system clock d) Receiver clock 41. input controls the rate at which the character is to be received. a) System clock b) Transmitter clock c) Bus system clock d) Receiver clock

10 ANSWER: d MCQ From PICT College of Engineering 42. may be used as a general purpose one bit inverting input port. a) DSR b) DTR c) RTS d) CTS 43. may be used as a general purpose one bit inverting output port. a) DSR b) DTR c) RTS d) CTS 44. pin of 8251A receives a composite stream of the data to be received by 8251A a) RXD b) RXC c) RXRDY d) RD 45. When a data character is sent to 8251A by the CPU, it adds start bits prior to the serial data bits, followed by optional parity bit and stop bits using the mode instruction control word format. a) Synchronous b) Asynchronous c) Both a & b d) None of the above

11 46. In the character synchronization can be achieved internally or externally. a) Synchronous b) Asynchronous c) Both a & b d) None of the above 47. Once the mode instruction has been written into 8251A and SYNC characters are inserted internally by 8251A, all the further control words written with will load command instruction. a) C/D=0 b) C/D=1 c) C /D=1 d) C/D =1 ANSWER: d 48. O/P also may be used as a general purpose one bit inverting O/P port that can be programmed low to indicate the modem. a) RTS b) DTR c) CTS d) All of the above 49. is used to generate internal device timings and normally connected to clock generator. a) CLK b) CLK reset c) CLK set d) None

12 50. is active low input to 8251A is used to inform it that the CPU is reading either data or status information from its internal register. a) RD b) BD c) CS d) WR

13 Q1)In scaned sensor matrix mode, it generates if a change in sensor value is detected at the end of sensor matrix scan. (a)irq (b)cntl/stb (c)stb (d)cs Q2)Display RAM is of bits. (a)8x16 (b)16x16 (c)16x8 (d)8x8 Ans: (c) Q3)In the decoded mode, the 8279 uses only location. (a)first 4 (b)first 8 (c)last 8 (d)last 4 Q4)In the encoded mode, the 8279 uses location. (a)first 4 (b)first 8 (c)all location (d)bboth (b)&(c) Ans: (d) Q5)Following are mode for Scan counter. (a)encodede (b)decoded (c) Both (a)&(b) (d)any one Ans: (c) Q6)In the encoded mode, it provides a bit binary count on scan lines (SL0-SL3). (a)3 or 4 (b)4 or 8 (c)8 (d)4 Q7) 8279 provides command words. (a)4 (b)8 (c)16 (d)12 Ans: (b) Q8)All the 8 command words of 8279can be read or written with.

14 (a)cs=0 Ao=1 and on rising edge of WR. (b) CS=0 Ao=1 and on trailing edge of WR. (c) CS=0 Ao=1 and on rising edge of RD. (d) CS=0 Ao=1 and on trailing edge of RD. Q9) command is used for programming the operating mode of keyboard & display section. (a)keyboard/display Mode Set Command (b)program Clock Command (c)read FIFO/Sensor RAM Command (d)red Display RAM Command Q10) Keyboard/Display Mode Set Command, Keyboard mode is represented by. (a) 3 MSB, 2 LSB (b) 3 LSB, preceding 2 bit (c) 2 LSB, preceding 2 bit (d) 3 LSB, 5MSB Ans: (b) Q11)The 8279 command word for keyboard/display mode for encoded scan keyboard with two key lookout & 8 digit, 8 character display right entry is. (a) (b) (c) (d) Q12) command is used to read display RAM. (a)read Display RAM (b)program Clock (c)keyboard (d)none

15 Q13) command is used to write character into the display RAM. (a)read Display RAM (b)program Clock (c)keyboard (d)write Display RAM Ans: (d) Q14) command is used to inhabit or blank the display. (a)read Display RAM (b) Display Write Inhabit/Blanking (c)keyboard (d) Write Display RAM Ans: (b) Q15) command is used to set clear or blanking code of display and clear register status. (a)clear Command (b) Display Write Inhabit/Blanking (c)keyboard (d) Write Display RAM Q16) command disables IQR signal and enables further writing into RAM. (a)clear Command (b) Error Mode Set (c)keyboard (d) Write Display RAM Ans: (b) Q17)In sensor matrix mode, Error Mode Set command act as an. (a)end Interupt Command (b)write Display RAM (c)display Write Inhabit/Blanking (d)none Q18)The FIFO status word is used in the keyboard and mode. (a)strobed input (b)n-key rollover (c) scaned Sensor Matrix Mode (d) None

16 Q19)Whenever an empty FIFO is read by the microprocessor, an error is detected. (a)underrun (b)overrun (c)sensor closure error (d)parity error Q20)Whenever an attempt is done to write into a full FIFO an error is detected. (a)underrun (b)overrun (c)sensor closure error (d)parity error Ans: (b) Q21)Maximum keyboard size in encoded scan mode is keys. (a)16 (b)32 (c)8 (d)64 Ans: (d) Q22)Total characters recognized in encoded scan mode is. (a)128 (b)256 (c)512 (d)1024 Ans: (b) Q23)Maximum keyboard size in decoded scan mode is keys. (a)16 (b)32 (c)8 (d)64 Ans: (b) Q24)Total characters recognized in decoded scan mode is. (a)128 (b)256 (c)512 (d)1024 Q25) mode, one key must be released before another key will press will be detected and processed. (a)2-key look-out (b)n-key rollover (c)n-key lock-out (d)all of these Q26. Which display mode is similar to calculator type?

17 (a)left entry (b)right entry (c)autoincrement (d)none of these [ans=b] Q27. Which display mode is similar to typewriter type? (a)left entry (b)right entry (c)autoincrement (d)none of these [ans=a] Q28. In which mode, simultaneous key depression is not allowed? (a)scanned sensor matrix (b)n-key rollover (c)2-key lockout (d)none of these [ans=c] Q29. In which mode, each key depression is treated independently from all others? (a)scanned sensor matrix (b)n-key rollover (c)2-key lockout (d)none of these [ans=b] Q30. When the CD1CD0 bits are, the clear command selects blanking code for alphanumeric displays. (a)0 x (b)10 (c)11 (d)none of these [ans=b] Q31. For common code displays, the clear command of 8279A configure CD1CD0= (a)0 x (b)10 (c)11 (d)can not predict [ans=c] Q32. bits of clear command are used to select the blanking code for (a)cd0-cd1 (b)cf (c)ca (d)all of the above

18 [ans=a] Q33. Value of B7 B6 B5 for clear command of 8279 is (a)100 (b)101 (c)110 (d)111 [ans=c] Q34. bits of display write inhibit/blanking command of 8279A are used to blank the individual nibbles. (a)bl (b)iw (c)both (a) and (b) (d)none of these [ans=a] Q35. The values of B7 B6 B5 bits for display write inhibit/blanking mode of 8279A is (a)100 (b)101 (c)110 (d)111 [ans=b] Q36. If B4=1 of write display RAM mode of 8279A, mode is enabled. (a)autodecrement (b)autoincrement (c)both (a) and (b) (d) (a) or (b) [ans=b] Q37. When B7 B6 B5=100,8279A selects. (a)read FIFO/Sensor RAM mode (b)read display RAM mode (c)write display RAM mode (d)display write inhibit/blanking mode [Ans=c] Q38. The four LSBs specific the address of display RAM in read display RAM mode of 8279A.

19 (a)16 bit (b)16 byte (c)8 bit (d)8 byte [Ans=b] Q39. For read display RAM command of 8279A, the value of B7 B6 B5 is (a)001 (b)010 (c)011 (d)100 [Ans=c] Q40. When B7 B6 B5=010, 8279A is set in (a)read display RAM mode (b)read FIFO/Sensor RAM mode (c)program clock mode (d)keyboard/display mode [Ans=b] Q41. Value of B7 B6 B5 bits for program clock command is (a)001 (b)100 (c)010 (d)101 [Ans=a] Q42. Command words are loaded to 8279 on rising edge of (a)clk (b)wr (c)rd (d)irq [Ans=b] Q43. Command words are sent to data bus along with and. (a)cs=0, A0=0 (b)cs=0, A0=1 (c)cs=1, A0=0 (d)cs=1, A0=1 [Ans=b] Q44. In the right entry mode of 8279, the entry of next character is displayed by (a)left shifting display by one character (b)right shifting display by one character

20 (c)left shifting display by two character (d)right shifting display by two character [Ans=a] Q45. In left entry mode of 8279, if autoincrement flag is set to 1, then after each write operation display RAM address. (a)is decremented by 1 (b)is incremented by 1 (c)is decremented by 2 (d)remains unchanged [Ans=b] Q46. The data is entered at the rising edge of CNTL/STB signal in of (a)scanned keyboard (b)scanned sensor matrix (c)strobed input mode (d)all of the above [Ans=c] Q47. In the encode mode of 8279, the size of sensor matrix is whereas that in decoded mode is each. (a)8 x 4, 8 x 4 (b)8 x 8, 8 x 8 (c)8 x 8, 8 x 4 (d)8 x 4, 8 x 8 [Ans=c] Q can recognize different characters in decoded scan. (a)14 (b)49 (c)128 (d)7

21 [Ans=c] Q can rrecognize different character in encoded scan. (a)8 (b)64 (c)256 (d)16 [Ans=c] Q50. In keyboard scan of 8279, maximum size of keyboard is. (a)16 x 4 (b)8 x 4 (c)4 x 4 (d)8 x 8 [Ans=b]

Q1)In scaned sensor matrix mode, it generates if a change in sensor value is detected at the end of sensor matrix scan.

Q1)In scaned sensor matrix mode, it generates if a change in sensor value is detected at the end of sensor matrix scan. (a)irq (b)cntl/stb (c)stb (d)cs Q2)Display RAM is of bits. (a)8x16 (b)16x16 (c)16x8