Introduction to Innovus
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1 Introduction to Innovus Courtesy of Dr. Dae Hyun +1 (479)
2 Introduction to Innovus Innovus was called Innovus before v15 Standard Placement and Routing Tool from Cadence Download and unpack Innovus.tgz from course website We use Nangate 45nm library based on FreePDK45 We will follow a tutorial designed by my colleague Dr. Kim VQS64_4_fm as an example Lab5: pmul32_4_fm 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 2
3 What We Are Going To Do Chip outlining P/G network design Placement Pre-CTS optimization CTS Post-CTS optimization Routing Post-routing optimization Fill insertion 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 3 3
4 Chip Outlining Benchmark VQS64_4 (four-input 64-bit pipelined quick sort) input [63:0] mx1, mx2, mx3, mx4 input mclk output [63:0] my1, my2, my3, my4 mx1 rc1 my1 mx2 rc2 my2 mx3 rc3 my3 mx4 rc4 Level 0 Level 1 Level 2 my4 Registers Comparators 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 4 4
5 Chip Outlining VQS64_4_fm.globals init_pwr_net: Power nets. init_gnd_net: Ground nets. init_lef_file: Physical library files. init_mmmc_file: Multi-mode multi-corner analysis view files. init_verilog: Verilog netlists. VQS64_4_fm.view create_rc_corner: Capacitance table + RC analysis corner create_library_set: Library files create_constraint_mode: Constraint files create_delay_corner: Library + RC corner create_analysis_view: Analysis view set_analysis_view: Setup and hold analysis view 5 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 5
6 Chip Outlining Initialize % initrc invs171 Run Innovus. % innovus 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 6 6
7 Chip Outlining Click File Import Design. In the Design Import window, click Load and choose VQS64_4_m.globals. This will automatically fill up the settings. Then, click OK. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 7 7
8 Chip Outlining See the terminal for messages. There might be some Error or Warning messages. In the Innovus main window, press f to see the outline of the layout. Innovus automatically computes and prepares the layout area. In the main window, click Floorplan Specify Floorplan. Set the core utilization to 0.6. Set the core-to-left, core-to-top, core-to-right, and core-to-bottom to 5.0. Then, click OK. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 8 8
9 Chip Outlining 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 9 9
10 Chip Outlining Now, you will see the following window. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 10 10
11 Save Let s save the current design. In the terminal, run the following command to save the current design into test_01_floorplan.enc. savedesign test_01_floorplan.enc Later on, you can load the design as follows. When you launch innovus, add the following option to load the specified design. innovus -init test_01_floorplan.enc or, after you launch Innovus, run the following command. source test_01_floorplan.enc 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 11
12 P/G Network Design Click Power Power Planning Add Rings. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 12
13 P/G Network Design Fill in the input boxes as shown in the previous page and click OK. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 13
14 P/G Network Design Click Route Special Route. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 14
15 P/G Network Design P/G network 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 15
16 Placement Let s place the instances (cells). In the main window, click Place Place Standard Cell. In the following window, turn off Include Pre-Place Optimization. Then, click OK to run Placement. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 16
17 Placement It shows placement and trialroute results. See the terminal. It shows some more information. Total wire length: 46,920um Save it. savedesign test_03_pl.enc 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 17 18
18 Visibility Let s see the placement result only. Turn off the following check-box to turn off the visibility of the wires. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 18 19
19 Timing Analysis Run the following command to turn off SI-awareness. setdelaycalmode -siaware false Then, run the following command to analyze setup time. timedesign -prects It will show the following summary: 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 19 20
20 Timing Analysis Timing Summary Primary inputs in2reg in2out reg2reg reg2out Primary outputs Reg Setup time analysis Design Rule Violations 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 20
21 Timing Analysis Run the following command to check the longest path. report_timing 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 21
22 Pre-CTS Optimization Run the following command to optimize the design before CTS. ECO->Optimize Design (choose Pre-CTS stage) optdesign -prects This will take some time, depending on the machine 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 22
23 Pre-CTS Optimization Pre-CTS optimization Report Positive WNS The density increased from 60% to 75%. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 23
24 Clock Tree Synthesis (CTS) Open VQS64_4_fm.ctstch in a text editor and see the spec. Run the following command to run CTS. clockdesign -specfile VQS64_4_fm.ctstch - outdir clk_report 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 24
25 5. Clock Tree Synthesis (CTS) CTS " Sinks (64 F/Fs*12 groups = 768) " buffers inserted " levels Clock skew 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 25
26 Clock Tree Synthesis (CTS) You can see the clock tree by the following command: displayclocktree -clk mclk -level 1 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 26
27 Timing Analysis Run the following command to check timing. timedesign -postcts 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 27 30
28 Post-CTS Optimization Although we already satisfied the timing without any further optimization after CTS, we will run post-cts optimization. optdesign -postcts 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 28
29 Timing Analysis Run the following command to check timing. timedesign -postcts 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 29
30 Routing Click Route NanoRoute Route. Turn off Fix Antenna and click OK to run routing. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 30
31 Routing Routing result. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 31 35
32 Routing Routing result. Wirelength: 52,077um No DRC violations. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 32
33 Timing Analysis Run the following command to check timing. timedesign -postroute 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 33
34 Post-Routing Optimization Although we already satisfied the timing without any further optimization after routing, we will run post-routing optimization. setanalysismode -analysistype onchipvariation optdesign -postroute 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 34
35 Post-Routing Optimization Optimize Design 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 35
36 Fill Insertion Click Route Metal Fill Setup. Click Load and choose metalfill.cmd to load the setting I made. Click OK. Click Route Metal Fill Add. Click OK to insert metal fills. 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 36
37 Fill Insertion The following shows fill insertion result 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 37
38 Timing Analysis Run the following command to analyze timing. timedesign -postroute 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 38
39 Save Design Save final timing report report_timing Save final design File->Save Save Netlist File->Save->Netlist Save DEF File->Save->DEF 11/1/2017 CSCE/ELEG 4914: Advnaced Digital Design 39
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