WLSI Extends Si Processing and Supports Moore s Law. Douglas Yu TSMC R&D,

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1 WLSI Extends Si Processing and Supports Moore s Law Douglas Yu TSMC R&D, chyu@tsmc.com SiP Summit, Semicon Taiwan, Taipei, Taiwan, Sep. 9 th, 2016

2 Introduction Moore s Law Challenges Heterogeneous Integration WLSI Innovation and Implementation WLSI for HPC WLSI for Mobile and others Si Process and Moore s Law Si Process Extend from IC to System Moore s Law Extension from SoC to SiP Conclusion WLSI Outline 1

3 Moore s Law Challenges 2 Credit: Economist, 2016

4 Yield Cost Saving Process Cost depends on intrinsic cost and yield. Chip-partition/Split-dies into smaller dies reduce cost. Yield (cost) difference increases with D0 / chip size mm^2 (0.25X) mm^2 (0.33X) mm^2 (0.5X) 120mm^2 (1X) D0

5 From SoC- to SiP-Scaling WLSI Extends Moore s Law SoC SiP B A C D E 2D D B A C E Advantages Shorter interconnect, higher performance/power Smaller form factor Cost and cycle-time reduction 3D D A C E B 4

6 Introduction Moore s Law Challenges Heterogeneous Integration WLSI Innovation and Implementation WLSI for HPC WLSI for Mobile and others Si Process and Moore s Law Si Process Extend from IC to System Moore s Law Extension from SoC to SiP Conclusion WLSI Outline 5

7 I/O to Substrate and/or PCB TSMC WLSI Technology Sets Industry SiP New Trends Security C InFO (FOWLP) Mobile, Consumer, HPC Small form-factor Cost competitive CoWoS TM 2.5D/3D HPC, SoC partition Very high memory BW Wide envelope 6 UFI (WLCSP) Die/PKG size (mm 2 ) CoWoS- D. Yu, 2011 Semicon Taiwan, 3D-IC Technology Forum InFO- D. Yu, 2012 imaps Device Package Conference, Scottsdale, Az UFI: D. Yu, 3DIC Forum, 2014 ISSCC, San Francisco, Ca

8 WLSI Technology Platform Initiative, Innovation and Implementation 1 st to deliver Si Interposer (2.5D), CoWoS TM, for HPC 1 st to propose and realize 2D/3D high performance FOWLP, InFO and InFO_PoP, for mobile/iot. A game changer. 1 st System Integration Foundry- a new paradigm shift. 7

9 Si Interposer Milestones 1 st Wave Product Xilinx 7V2000T Xilinx 7VH580T Altera 3DTV1 Package view Logic x4 Logic1 x2 Logic2 x1 Logic x1 SRAM x1 Interposer size 775 mm 2 (25x31) 500mm 2 (25x20) 725mm 2 (25x29) Production May 12, TSMC Oct. 12, TSMC Oct. 12, TSMC Lead industry to introduce Si Interposer. Homogeneous and Heterogeneous Integration. Enables both Split-dies and Chip-partition to support Moore s Law extension. 8

10 Si Interposer Milestones 2 nd Wave Product Xilinx VU440 AMD Fiji Nvidia GP100 Logic x3 Logic x1 HBM1 x4 Logic x1 HBM2 x4 Package view Interposer size 1150 mm 2 (31x36) 1010mm 2 (28x36) 1160mm 2 (29x40) Production Jan. 15, TSMC Jun. 15, ASE/UMC Apr. 16, TSMC Exceeded full scanner size. Enable Logic + HBM1/2 integration for HPC. Scale-up SiP function and performance for deep learning and more. 9

11 Sub-mm interconnect DD Cu, lines/mm Small via, easy routing Very low defect density Super large size 1200 mm 2 in production. Going 1500 mm 2 CoWoS Key Merits Highest level of multi-die integration Flexible Integration JESD235 compatible for HBM. NO customization need. Enable Logic Chip-partition. Leverage Flip-Chip No ELK related CPI issue Same thermal solution as flip chip DD Interposer SiP ~40 mm SAP ~30 mm 10

12 InFO-PoP: Si Process Extention 1 st HD/HP 3D-FOWLP proposed, developed and delivered. Chips and function extended with molding. Si process extended and help to sustain Moore s Law. NOT embedded. Chip backside exposed with Form Factor, Heat Dissipation, CT and Cost advantages (Chip-first approach). Logic Substrate Logic I/Os Logic Molding and Metal Flip Chip CSP Package I/Os InFO Through- Mold Via (TMV) DRAM Logic substrate Logic or DRAM, Die or PKG Logic Through- InFO Via (TIV) Flip Chip PoP InFO-PoP SoC1 SoC2 Substrate SoC1 SoC2 11 Multi-Chip Flip Chip CSP Multi-Chip InFO

13 InFO_PoP for AP/DRAM Integrated design and manufacturing (Si System). High-end AP/DRAM applications with PPPCC optimization. 12

14 AP/DRAM SiP InFO/TIV Replaces 3DIC/TSV Architecture FC_PoP 3DIC (TSV) InFO_PoP Max. Bandwidth L H H Total Power H L L Thickness H M L Thermal qja (SoC) M H L Cost L H L Chip Partition N N Y DRAM KGP Y N Y - Doug Yu, 2014 IEDM, San Francisco, CA 13

15 Introduction Moore s Law Challenges Heterogeneous Integration WLSI Innovation and Implementation WLSI for HPC WLSI for Mobile and others Si Process and Moore s Law Si Process Extend from IC to System Moore s Law Extension from SoC to SiP Conclusion WLSI Outline 14

16 WLSI for Advanced Packaging Si Process Extension Extended Si System process flow Integrated Design and Manufacturing Grand optimization of multi-component system Moore s Law Extension Enable SiP-Scaling, complementary or alternative to SoC-Scaling System Volume Scaling Down, Function Scaling Up Full IO pin-count spectrum: mobility, IoT, automotive, HPC and DRAM integration. 15

17 WLSI Leverage/Extend Si Process CoWoS Si with TSV (Interposer) CoW Stacking (m-bump) Dicing, Mount on Substrate Ship Interposer wafer CoW CoWoS InFO_PoP Fan-out With TIV PoW Stacking (with BGA) Dicing and Ship Fan-out wafer PoW CoWoS: CoW, Chips stack on TSV wafer. InFO_PoP: PoW, PKG stack on TiV wafer. Manufacturing of HD/HP 3D-FOWLP and CoWoS is very challenging. WLSI leverages on-chip Cu interconnect technology. Extends Si wafer processing from Si to (sub) System. 16

18 SiP-Scaling Reduce System Size and Increase Function DRAM Logic Flash RF Passives More functions Higher Performance Smaller, cheaper with lower power Silicon Interposer CIS Analog MEMS PCB for system integration WLSI for heterogeneous integrationmulti-chips integrated In a single package 17

19 Compact 2D Integration For Chip Partition and HPC Finer pitches RDL (L/S=2/2mm) Multi-Chip ultra-large PKG 24x26mm 2 Die-1 Die-2 Die-3 18

20 Compact 3D-Stacking for Extension of Moore s Law High-density multi-chips 2D-Stacking High-density multi-layers 3D-Stacking 3D-Stacking Layout Multi-chips Integrated Package 19

21 Compact 3D-Stacking Realizes Intelligent Systems Multi-chips, multi-sensors intelligent systems Scheme Intelligent System Chip 1 Chip 2 Sensor 1 Sensor 2 Heart Rate Sensor Pulse Rate: 4/3.44x60 = 70 (beats/min) 20

22 2013 TSMC, Ltd 16nm 20nm 28nm 40nm 65/55nm 90/80nm 0.13µm 0.18µm 0.25µm 0.35µm Moore s Law Platform ESF3 ESF2 ESF1 Automot ive Expanding Functionality MEMS Embedded Embedded Analog Logic Flash DRAM (MCU) Foundry Tech Platforms HK/MG Immer Low-R sion Cu/EL K Strai neds ilico Cu/ n LK 12 BSI 8 BSI Expanding Functionality MS/RF Power High CMOS CMOS IC-BCD Voltage Image Sensor 28nm 40nm 65nm 90nm 0.13µm 0.18µm 0.25µm 0.35µm >0.5µm M MEMS WLSI Platform More-Than-Moore Platform M R A E-Flash E-DRAM Mixed Logic (MCU) Signal/RF B C BCD CIS Power IC D HV Driver 20nm 28nm 40nm 65nm 90nm 0.13µm 0.18µm 0.25µm 0.35µm 21 FC-BGA FC-CSP Cu_BoP Cu_BoT Fan-In WLP InFO Bumping EU/LF/Cu TSV InFO_PoP TSV 3D- Interposer IC

23 3D WLSI WLSI Optimization and Heterogeneous Integration SoC SiP Grand Optimization 22

24 WLSI Conclusions 1 st to commercialize Si Interposer, and 1 st to bring propose and bring 3D-FOWLP to HVM. Grow TSMC to 1 st SiP-foundry. WLSI extends Si process to system and enables SiP-Scaling, to support Moore's Law extension. Grand system optimization of Moore s Law and MTM chips with WLSI provides unique values. Further strengthen TSMC as wafer processing technology powerhouse. 23