L évolution des architectures et des technologies d intégration des circuits intégrés dans les Data centers

Transcription

1 I N S T I T U T D E R E C H E R C H E T E C H N O L O G I Q U E L évolution des architectures et des technologies d intégration des circuits intégrés dans les Data centers 10/04/2017 Les Rendez-vous de l'irt Denis Dutoit

2 Outline A supercomputer today. Application landscape and server architecture evolution towards 3D integration. Some examples (state-of-the-art, IRT3D): 3D stacking for Data Centers. Interposer based integration for Data Centers. Conclusion. 10/04/2017 2

3 A supercomputer today Cluster Server DDR Storage CPU Blade Rack Rack Interconnect 10/04/2017 3

4 Application landscape and associated challenges Numerical simulation Data Analytics WEB servers State of the art FLOPS (peak) 15 MW 6 GFLOPS/W > 10M cores 5.6 Zettabytes in pj/bit servers services Computing performance, Parallelism, Energy efficiency. Data deluge Data movement energy Shared resources Target 2020: x10 energy efficiency Exaflops: FLOPS 20 MW 50 GFLOPS/W ~1 pj/bit GIGA TERA PETA EXA ZETTA /04/2017 4

5 Server system architecture Numerical simulation Data Analytics WEB servers Processor Memory / Storage Today: 10 pj/bit 3D integration: 1 pj/bit Room for 3D Integration? YES Interconnect Today server system architecture 10/04/2017 5

6 3D Integration Leti 3D Contact : Die-to-die Through-Silicon-Via (TSV) Pitch Diameter TSV + µbump Diameter: 10 µm Pitch : 20 µm Cu-Cu Diameter : 1.7 µm Pitch : 3.4 µm HD-TSV Diameter : 0.85 µm Pitch : 1.75 µm Monolithic 3D (CoolCube TM ) Diameter: 0.05 µm Pitch : 0.11 µm ~10 3 3D Contacts / mm² SoC Level Integration Interposer ~10 5 3D Contacts / mm² Core-/Block-Level Integration D Contacts / mm² Gate-/Transistor-Level Integration 3D Stacking 17/05/2017 6

7 3D Integration leverages new computing architectures Numerical simulation Data Analytics WEB servers Processor Memory / Storage Many-cores, Heterogeneity (GPU, FPGA). Interposer integration 3D Memories. 3D stacking Deep learning, Processing in Memory (PIM). High density 3D and monolithic 3D Hyperconverged architecture: Server on a chip. Interposer based integration Interconnect From rack-to-rack to chip-to-chip. Photonic interposer integration 10/04/2017 7

8 3D stacking - Example Numerical simulation Data Analytics WEB servers Processor Memory / Storage 3D Memories. 3D stacking Deep learning, Processing in Memory (PIM). High density 3D and monolithic 3D Interconnect 10/04/2017 8

9 3D NOC (2015): 3D stacking demonstrator from IRT Extending Network-on-Chip to the third dimension Die-to-die energy efficiency : Die on package on board: 10 pj/b 3D Stacking with 3D NoC: 0.66 pj/b Cmos Process 3D Tech. Package Complexity 65nm STMicroelectronics, Low-Power, Multi-VT TSV middle (AR 1:8) CEA-LETI µ-bumps, 50µm x 40µm pitch Face2Back stacking, Die2Die assembly 12x12x1.2 flip-chip package, 4 layers substrate 1.63 Mbyte SRAM, 228 Mtransistors, 276 IOs BEOL top die µ-bump TSV AR 1:8 BEOL bottom die C4 bump Package ball Bottom die photo (72 mm 2 ) 3D TSV pitch, 40µmx40µm Molding Package Substrate Top die Bottom die 3D cross section 10/04/2017 9

10 Interposer based integration - Examples Numerical simulation Data Analytics WEB servers Processor Many-cores, Heterogeneity (GPU, FPGA). Memory / Storage Interposer integration 3D Memories. 3D stacking Hyperconverged architecture: Server on a chip. Interposer based integration Interconnect 10/04/

11 High Bandwidth Memory (HBM) integration with processors FPGA Altera integrates HBM2 memories from SK hynix in Stratix 10 products, Integration is performed thanks to the EMIB (Embedded Multidie Interconnect Bridge) from Intel. GPU NVIDIA integrates HBM2 memory from Samsung in the Pascal GPU module. 10/04/

12 INTACT demonstrator (2017): Active interposer from IRT Active Interposer for many-cores: 96 cores compute fabric Heterogeneous 3D partitioning for high energy efficiency and reduced cost 28nm FDSOI chiplets (x6) Low Power Compute Fabric Wide Voltage Range (0.6V 1.2V) Body Biasing for logic boost & leakage ctrl 65nm Active Interposer Power unit (Switched Cap DC-DC conv.) Interconnect (Network-on-Chip) Test, clocking, thermal sensors, etc Performance Targets 100 GOPS 10 GOPS/Watt 25 Watts total Cache Coherent Compute Fabric 96 cores (MIPS-32bit) L1/L2/L3 coherent caches Implemented with 3D-Plugs Full support of Linux OS TSV Ø 10µm Height 100µm µ-bumps Ø 10 µm Pitch 20 µm Symposium DIC 2015 ISVLSI /04/

13 Conclusion Fundamental change to Data Center system architecture: Demand for increased performance and data capacity, But constraints on energy consumption and cost. DDR Storage CPU Server Towards emerging integration technologies: 3D stacking, Interposer, Improve capacity, energy and TCO. IRT 3D demonstrators pave the way towards a highly energyefficient and highly integrated compute node for the Exascale revolution. 10/04/

14 Merci de votre attention 10/04/