Analyze system performance using IWB. Interconnect Workbench Dave Huang

Transcription

1 Analyze system performance using IWB Interconnect Workbench Dave Huang 1

2 Information Personal peech of personal experience I am on behalf on myself

3 Interconnects Are at the Heart of odern ocs Verification Challenges: Checking system behavior Point to point data integrity Verify system behavior Quad Core Cortex -A15 Quad Core Cortex -A15 Understanding system scenarios anage data flow from multiple protocols Concurrent scenarios Cover all system scenarios Validate system performance

4 Analyzing Performance : Influence Quad core Cortex-A15 ACE ADB b ACE GIC-400 Quad core Cortex-A7 ACE ACE ali-t604 Graphics ADB-400 U b ACE-Lite + DV Coherent I/O device ADB-400 U b CoreLink CCI-400 Cache Coherent Interconnect 128 up to 0.5 Cortex-A15 frequency ACE-Lite 128b ACE-Lite PHY ADB b DDR3/2 LPDDR2 DC-400 ACE-Lite ACE-Lite 128b ACE-Lite PHY DDR3/2 LPDDR2 ACE-Lite + DV ACE-Lite 128b AXI4 Other laves DA AXI4 128b NIC-400 NIC-400 Configurable: AXI4/AXI3/AHB/APB Other laves LCD Configurable: AXI4/AXI3/AHB U-400 ACE-Lite + DV Thin Link Focus for performance of a path requires us to consider other masters that may influence the delay Hardware influences : performance. Thin links, NIC-400 Thin links, NIC-400 configuration, configuration, L2 Qo, cache L2 L2 peed, Cache cache DDR peed, Controller DDR Controller speed. speed. cenario influences : Local traffic conflict, ACE-Lite Traffic, Processor Activity odeling all these HW artifacts in TL is impractical. Accurate performance analysis must therefore use cycle-accurate RTL models

5 Cadence Interconnect Workbench Pre-integration Cycle-accurate Performance Analysis and Verification ystem IP Data UV Testbench Performance GUI CoreLink 400 ystem IP RTL & IP-XACT IP-specific Traffic Profiles Cadence VIP Library for ABA Interconnect Workbench Assembly anual oc Testbench oc Traffic Testbench Incisive Interconnect Workbench Analysis & Debug Performance easurements Performance Analysis Verification Closure Tune Architecture For Interconnect IP Integration Performance of use case traffic loads Verify configuration functionality For oc Integration Validate performance in context of IPs Benefits Ø horten performance tuning and analysis iteration loop from days to hours Ø Reduce testbench development time from weeks to hours

6 Cadence Interconnect Workbench Automated Testbench Assembly for CoreLink 400 ystem IP Architectural Information UV Testbench Testsuite CoreLink 400 ystem IP RTL & IP-XACT Interconnect Workbench Assembly vplan ABA Designer imvision config Cadence ABA VIP Library cripts User Configuration

7 IWB Generate Operation (Verification Testbench) <prefix>_nic400_mp5x8_(env tb) clk rst tb _nic400_mp5x8 clk rst tarting IWB: IWB: (c) Copyright 2012 Cadence... ######## IWB CONFIGURATION ######### library path set to project_libraries library name set to iva_nic400_mp5x8 XL file path set to <...>/nic400_mp5x8.xml target path set to fabric_target package prefix set to iva platform configured to UV_E I ###### TARTING GENERATION FLOW ####### ######### IPORTING THE DUT ########### ##### BUILDING THE HDL TETBENCH ###### ##### BUILDING THE UV TETBENCH ###### PAIVE Agent ACTIVE Agent RTL-shell AXI4 aster/lave Interface AXI3 aster/lave Interface AHB-Lite aster/lave Interface APB aster/lave Interface

8 IWB Generate Operation (Performance Testbench) <prefix>_nic400_mp5x8_(env tb) clk rst tb _nic400_mp5x8 clk rst tarting IWB: IWB: (c) Copyright 2012 Cadence... ######## IWB CONFIGURATION ######### library path set to project_libraries library name set to iva_nic400_mp5x8 XL file path set to <...>/nic400_mp5x8.xml target path set to fabric_target package prefix set to iva platform configured to UV_E I ###### TARTING GENERATION FLOW ####### ######### IPORTING THE DUT ########### ##### BUILDING THE HDL TETBENCH ###### ##### BUILDING THE UV TETBENCH ###### ### GENERATING VERIFICATION CONTENT ### ###### GENERATION FLOW COPLETE ####### Verification Content UV e/v Testbench VIP Configuration vplan (Perf) Test uite PAIVE Agent ACTIVE Agent RTL-shell Performance Generator AXI4 aster/lave Interface AXI3 aster/lave Interface AHB-Lite aster/lave Interface APB aster/lave Interface

9 Generate Interconnect Testbench RTL HVL CoreLink ABA Designer Generate Cascaded Interconnect NIC-400 Interconnect Workbench Testbench Generation CCI-400 VIP eta-data Library ystem Development uite Functional Verification Platform Incisive Verification Computing Platform Palladium XP

10 Generate Interconnect Testbench RTL HVL CoreLink ABA Designer Cascaded Interconnect Interconnect Workbench Testbench Generation IP-XACT Generate CCI-400 NIC-400 VIP eta-data Library Generated Testbench ystem Development uite Functional Verification Platform Incisive Verification Computing Platform Palladium XP

11 Generate Interconnect Testbench RTL HVL CoreLink ABA Designer Performance etrics Verification etrics VIP Cascaded Interconnect Interconnect Workbench IP-XACT IC NIC-400 Testbench Generation Generate IC CCI-400 VIP eta-data Library Virtual equence Routing odel Generated Testbench ystem Development uite Functional Verification Platform Incisive Verification Computing Platform Palladium XP

12 Cadence Interconnect Workbench Automated Testbench with Normal IWB flow Architectural Information UV Testbench Testsuite CoreLink 400 ystem IP RTL & IP-XACT Interconnect Workbench Assembly vplan ABA Designer imvision config Cadence ABA VIP Library cripts User Configuration

13 Cadence Interconnect Workbench Automated Testbench with New IWB Flow Architectural Information UV Testbench Testsuite eta Data file Interconnect Workbench Assembly vplan tandard Format imvision config Cadence ABA VIP Library cripts User Configuration

14 Why is A New Flow Needed? odified ABA buses are used to save power consumption and improve performance. Every customer has every specific feature on interconnect structure such as memory interleaving and (ABA + NOC). IP-XACT can t handle customized buses & specific interconnect structure.

15 How to Create Real Transactions? ost of masters(ultimedia IPs) generate periodic transactions at real working Read buffer Write buffer Require specific traffic generator to create periodic transactions Traffic ynthesizer can mimic the real master s working AXI Protocol Abstractor Traffic ynthesizer

16 cenarios for Performance Analysis Why is the user interested in the worst case scenario? Define Hardware pecification Need the various scenarios Look for optimized using modes considering DVF and Qo earch for an optimized interconnect structure. Various cenarios help the user find some weak points of bandwidth and latency.

17 Worst Case cenario Example 3D Graphics with caling (How many f/s?) PEG4 Video (How many f/s?) How many windows are overlaid? inchae On creen Characters with RotaCng Camera is working with caling (How many f/s?)

18 Which aster & lave are Concerned about Performance Analysis? CPU Cluster Cortex- A15 Cortex- A15 Cortex- A15 Cortex- A15 L2 Cache CPU Cluster Cortex- A7 Cortex- A7 Cortex- A7 Cortex- A7 L2 Cache GPU FC CAIF CI DI Ethernet Display UB2 UB3 ATA Typical Wireless AR based oc Coherent oc Interconnect emory Controller DDR3 emory Funnel Non-coherent oc Interconnect Peripheral Fabric ystem Boot UART INTC Timer ultimedia asters GPU : 3D Graphics FC : PEG4 Video Display : Overlay Windows CAIF : caling, Rotating, Camera Interface Typical AR based oc Performance of the emory Funnel is key to system performance lave : emory Controller

19 Information for Traffic ynthesizer Read fps bytes/sec Write fps bytes/sec arsize arlength awsize awlength aster words 4 4words 4 aster words 4 aster words 4 aster words 4 aster words 4 aster words 4 aster words 4 aster words 4 aster words 4 4words 4 aster words 4 4words 4 aster words 4 4words 4 aster words 4 aster words 4 aster words 4 aster words 4 aster words 4 aster words 4 4words 4 aster words 4 4words 4

20 How to Analyze Performance

21 Overview of IPA hows which slave is popular hows overall transaccon data

22 aximum Latency in the Worst cenario Points the maximum latency hows the detailed informacon hows the overlapped transaccons

23 Compare with different Qo values - ame aster & ame cenario Qo value is High Two different Runs Qo value is Low

24 Checks with User Definition - Latency Added User s Checks ViolaCon TransacCons Each ViolaCon TransacCon

25 Checks with User Definition - Bandwidth Added User s Checks ViolaCon TransacCons Each ViolaCon TransacCon

26 Checking Read Latency Hit/iss Cache Hit latency Cache iss Latency how the detailed InformaCon

27 ummary Interconnect Workbench for oc Interconnect Verification, Performance Analysis Performance easurement and Analysis for oc Interconnect Explore performance aspects across multiple simulations, multiple scenarios Qo, Outstanding Transactions, Issuing Rate, etc To optimize interconnect Topology, Qo cheme, Transaction Buffer Depths, etc Visualize cycle-accurate performance against a variety of scenarios Assess the effect of different traffic scenarios on performance Automated Verification of oc Interconnect Quickly configure verification environment to the interconnect Run out-of-the-box tests on the generated interconnect Easily update environment to verify changes imic Real Transactions with Traffic ynthesizer Easily generate periodic transactions Easily implement the worst case scenario and analyze the performance

28 Q&A