ARM the Company ARM the Research Collaborator

Transcription

1 UMIC Day 13 ARM the Company ARM the Research Collaborator John Goodacre Director Technology and Systems Aachen 15 th October

2 The ARM Vision A world where all electronic products and services are based upon energy efficient technology from ARM, making life better for everyone 2

3 ARM Overview ARM is the world s leading semiconductor IP company and The Architecture for the Digital World More than 25 billion ARM technology based chips shipped to date Unrivalled Partner ecosystem About 750 processor licenses sold to more than 250 companies Millions of developers; billions of users ARM has the right technology optimized for a mobilizing world and beyond 3

4 Unparalleled Applicability Cortex Architecture Profiles Compatibility across a diverse application range Cortex- A (Applications) Virtual addressing (MMU) for running Windows, Linux, etc Cache for high performance Often heavy focus on 3 rd party applications requiring large memory Cortex- R (Real-time and Control) No virtual address capability, typically run RTOS Microarchitecture focus on on fast response to interrupts ECC cache options, lock-stop, error tolerance Cortex- M (Microcontroller) Extremely small gate count and low power Fast and deterministic exception handing No cache, no virtual address capability Cortex-M4 SC300 Cortex-M3 Cortex-M1 SC GHz Cortex-A8 x1-4 Cortex-A5 1-2 x1-4 Cortex-A9 1-2 x1-4 Cortex-A15 Cortex-R7 Cortex-R5 Cortex-R4 Cortex-M0 12k gates... 4

5 Solutions For Each Price Point Volume (Mu) Maximum efficiency for the performance required and then add big.little Cortex-A57 Mali-T628 Cortex-A15 Mali-T604 Cortex-A9 Mali-400 Cortex-A9 Cortex-A9 Cortex -A8 Cortex-A7 Cortex-A5 ARM11 Mali-400 Mali TM -300 Cortex-A12 Cortex-A53 Mali-450 Mixture of ARM and Gartner Estimates Relative SoC die Size 5

6 Enhancing Design Efficiency Outpacing Moore s Law with micro-architectural innovation High-end smartphone 2011 Micro-architectural innovation + process shrink 1/5 th the Area Mass-market smartphone mm 2 per core Cortex -A9 processor 40nm, 1GHz Less than 1/3 rd the Power Matching performance ARM Cortex-A7 processor 28nm, 1.2GHz Development already extending to 16/14nm FinFET 6

7 Cortex-R4 High performance, real-time embedded processor Deterministic event response Configurable feature set Dependable system support Cortex-R5 (2010) New features to enhance system performance Low-latency peripheral port Data DMA coherency port Dual core configuration Extended error management Smaller Floating Point Unit Cortex-R7 (2011) Large performance increase Advanced micro-architecture Higher clock frequency Symmetric Multi-Processing Dual core and DMA coherent Quality of Service features Extended real-time memory Hard error management Integrated interrupt controller 7

8 ARM Cortex-M0+ Processor The most energy efficient 32-bit processor Processor consumption as under 10µA/MHz* Outstanding result of 2.15 CoreMark/MHz *TSMC90LP, 1.2V, min. configuration Extended design options Fast I/O Interface for single cycle access Micro Trace Buffer for faster debug MPU for safety related applications For entry-level application which requires more Battery life: Internet of Things (IoT) or sensors Advanced debug: as application complexity raise, e.g. comm. stacks Safety: factory automation or automotive 8

9 Developer Access to Cortex-M 9

10 Scalable Mali GPU solutions Performance Mali-400 MP First OpenGL ES 2.0 multicore GPU Scalable from 1 to 4 cores Low cost solution with Mali-300 Mali-300 OpenGL ES 2.0 compliant Mali-450 MP 2x Mali-400 performance Scalable up to 8 cores Leading OpenGL ES 2.0 performance Graphics Only Performance Optimized for tablets Mali-T628 50% performance uplift OpenGL ES 3.0 support Scalable to 8 cores Scalable to 2 cores Mali-T604 First Midgard architecture product OpenGL ES 3.0 support Scalable to 4 cores Mali-T678 High end solution Max compute capability Graphics and GPU Compute Mali-T624 50% performance uplift OpenGL ES 3.0 support Scalable to 4 cores Mali-T622 Smallest Full Profile GPU Compute Enables mid-range smartphone 50% more energy efficient than Mali-T604 10

11 The Mali Ecosystem 11

12 Integrating Efficient Compute GIC-400 Interrupt Control IO Coherent Masters Simplified view of complex processors Display and Video Subsystem Cortex-A15 Cortex-A7 Mali- T628 GPU Shader Shader Shader Coherency maximizes on-chip residency Shader Shader Shader L2 cache ADB-400 L2 L2 Cache ADB-400 ADB-400 L2 Cache ADB-400 Efficient Voltage scaling for power management MMU-400 MMU-400 MMU-400 MMU-400 CoreLink CCI-400 Cache Coherent Interconnect Common memory view for all SoC components TZC-400 DMC To Peripheral Interconnect Optimized path to memory for best performance DDR/LPDDR DDR/LPDDR 12

13 Efficiency at the Implementation Level POP IP Core-hardening acceleration technology Targeted to optimized Cortex CPU for power or performance POP IP Core-hardening acceleration technology Targeted to optimized Mali GPU for power or performance Standard Cells Multi-Vt cell libraries Multi-Channel cell libraries Multiple track height libraries Memory IP HS & Ultra-low Power Multiple power modes Multi-Vt options 13

14 big.little Processing Tightly coupled combination of two ARM CPU clusters: Cortex-A15 and Cortex-A7 - functionally identical Same programmers view, looks the same to OS and applications big.little combines high-performance and low power Automatically selects the right processor for the right job Redefines the efficiency/performance trade-off Highest computing performance Demanding tasks Always on, always connected tasks Significantly lower energy Current big.little smartphone processor big LITTLE Current big.little smartphone processor 14

15 Rethinking Computation Efficiency Right Processor for the Right Task CPU GPU Interconnect & memory sub system Latency Sensitive Bandwidth Sensitive Serial dominated Most Efficient Execution? Extremely parallel 15

16 Sub-system: Heterogeneous Compute + big.little AMBA Extensions Interface (Master) Cortex-A15 Cluster CPU 0 L2 Cache CPU 2 CPU 1 CPU 3 Cortex-A7 Cluster CPU 0 L2 Cache CPU 2 CPU 1 CPU 3 Mali T600 series GPU Shader Core 0 Shader Core 1 L2 Cache SMMU Shader Core 2 Shader Core 3 Debug & Trace NIC 400 CoreSight Resources Mgt System Power JTAG & Trace PMIC/ APB Bus Cache Coherent Interconnect (CCI-400) AMBA Extensions Interface (Master) DMC-400 LPDDR2/DDR3 Controller NIC 400 TrustZone enabled 2012 Compute Subsystem On-Chip Memories (RAM, ROM) Base Peripheral DDR PHY or DDR Memory AMBA Extensions Interface (Slave) 16

17 Summary of EU Project Participation Acronym Ref. Project Title Start Funding POWER (OMI) 6892 Portable Workstation for Education in Europe 1992 ESPRIT 3 DE-ARM (OMI) 6909 Embedded RISC macrocell 1992 ESPIRT 3 STANDARDS (OMI) 7267 Standards Methodology and Harmonisation for OMI 1992 ESPRIT 3 CASCADE 8670 Chip Architecture for Smart Cards and Portable Intelligent Devices 1993 ESPIRT 3 HIPERION (OMI) 9166 High-Performance Radio local-area Network 1993 ESPRIT 3 IMPROVE Introducing total quality management and business process mgmy into I.T. companies 1995 FP4-ESPRIT ASPIRE Advanced silicon prototyping in reconfigurable environments 1995 FP4-ESPRIT DE2 (OMI) Open microprocessor systems initiative for deeply embedded arm application macrocells 1995 FP4-ESPRIT ThEOS (OMI) Thumb support for EOS (RTOS) 1995 FP4-ESPIRT Asic4PMR Architecture for single chip for private mobile radio communication 1996 FP4-ESPRIT ATOM (OMI) Applications in Telecommunications for OMI Macrocells 1997 FP4-ESPRIT CODAC Co-design for applications with embedded cores 1997 FP4-ESPRIT INFOGATE Information gate for home FP4-ESPRIT PEOPLE Power Estimation for fast Exploration of Embedded systems 1998 FP4-ESPRIT G3CARD rd Generation Smartcard 1999 FP5-IST EPHEM Emulated Peripherals for High performance Microcontrollers 2001 FP5-IST POET Power Optimisation for Embedded SysTems 2001 FP5-IST REMUNE Methods and Tools for Telecom Systems 2001 FP5-IST SYDIC-Training System design industry council training 2002 FP5-IST HIPEAC 4408 High Performance Embedded Architectures and Compilers 2004 FP6-IST SPRINT Open SoC Design Platform for Reuse and Integration of IPs 2006 FP6-IST SOCRADES Service Oriented Cross-layer infrastructure for Distributed smart Embedded devices 2006 FP6-IST emuco Embedded Multi-Core Processing for Mobile Communication Systems 2008 FP7-ICT-2 REALITY Reliable and Variability tolerant SoC Design in More-Moore Technologies <=45nm 2008 FP7-ICT-2 HIPEAC High Performance and Embedded Architecture and Compilation 2008 FP7-ICT EUROCLOUD Energy-conscious 3D Server-on-Chip for Green Cloud Services 2009 FP7-ICT-4 ENCORE ENabling technologies for a programmable many-core 2009 FP7-ICT-4 SEPIA Secure Embedded Platform with advanced Process Isolation and Anonymity Capabilities 2009 FP7-ICT-5 MONTBLANC European scalable and power efficient HPC platform based on low-power technology 2011 FP7-ICT-7 VIRTICLE SW/HW extensions for virtualized heterogeneous multicore platforms 2011 FP7-ICT-7 CARP Correct and Efficient Accelerator Programming 2011 FP7-ICT , Montblanc II, EUROSERVER, SAVE 17

18 MontBlanc: FP7-7 A project that invests significantly to test and evaluate the ability of ARM based solutions to address the HPC market Involves both hardware prototyping and associated software to run and evaluate current mobile-devices in a HPC environment Key to ARM is the learning and requirement capture to enable and support next generation technology and partner solutions focused specifically at microserver based solutions for across enterprise, embedded and HPC markets 18

19 CARP: FP7-7 This is the first such collaborative project undertaken by ARM s media processor division (MPD) MPD is leveraging both the consortiums understanding regards the correctness of the accelerator based platform, but more importantly, that the automatic conversion of existing code can have a portable representation that will be appropriately accelerated on ARM based GP-GPU compute platforms The project is allowing ARM to look also at more advanced run-times for generic heterogeneous compute platforms (bl + GPGPU + accl) 19

20 Virtical: FP-7 This project is embracing the new ARM hardware extensions for virtualization and in effect answering the challenges posed by emuco Specifically, the work in KVM (Linux kernel based virtual machine) is enabling key business scenarios such as BOYD and content isolation. This enrichment of the software environment on devices, also lets ARM leverage the project to create and share across the world the new de-facto specification standard for ARM power control coordination Together, the consortium is building a EU based centre of expertise in embedded virtualization 20

21 Future Vision For Compute (personal) Software is constructed from series of specific phases, of differing granularity, that can be accelerated and/or more efficiently executed when using more code-specific hardware Phases identified statically at design/compilation or dynamically at runtime A phase aware runtime/scheduler with appropriate annotated intermediate representation can ensure task placement is temporally ideal A compute system will share a globally addressable global address space to allow any compute unit to register its specialized (heterogeneous) services to the application runtime A compute unit can use any virtually mapped location; all compute unit own a physical partition of the global address space; only one unit can cache a physical location; all accesses are made coherently through the cached owner unit Compute units of various types can be collected into a system through traditional SoC, or through new Silicon-on-silicon (3DIC) technologies Compute then becomes a challenge of data locality and connectivity 21

22 ARM Units for Compute Slave interface into unit s view of it s memory Access To DDR Local Peripherals Compute Unit Access to rest of SoC In a system, various ARM IP blocks enable the construction of a Compute Unit from a single Cortex-A5 up to a 16-way Cortex-A57 Such systems can support multiple software models due to supporting a coherent, virtually mappable memory across a global address space Eg Shared memory or message based Capable of remote (off chip) memory access latencies under 100ns 22

23 Slave interface from rest of SoC Sharing coherent view into compute unit s view of memory Cortex-A9 MPCore: The first Compute Unit ARM Coresight Multcore Debug and Trace Architecture FPU/NEON PTM I/F FPU/NEON PTM I/F FPU/NEON PTM I/F FPU/NEON PTM I/F Cortex-A9 CPU Cortex-A9 CPU Cortex-A9 CPU Cortex-A9 CPU Instruction Cache Data Cache Instruction Cache Data Cache Instruction Cache Data Cache Instruction Cache Data Cache Generalized Interrupt Control and Distribution Snoop Control Unit (SCU) Cache-2-Cache Transfers Snoop Filtering Advanced Bus Interface Unit Timers Accelerator Coherence Port Primary AMBA 3 64bit Interface Optional 2 nd I/F with Address Filtering Interface to local memory Master interface to remote memory 23

24 CoreLink CCI-400: big.little Compute Single Inner-coherent Region (SMP) Save interfaces from rest of SoC Sharing coherent view into compute unit s view of memory Quad Cortex- A57 Quad Cortex- A53 ACE Mali GPGPU Rest-of-SoC (Master) Interfaces to DDR memory L2 cache L2 cache CoreLink CCI-400 Cache Coherent Interconnect CoreLink DMC-400 DDR2/3 CoreLink DMC-400 PHY DDR2/3 Rest-of-SoC (Slave) Master interface into the rest of SoC and access remote memory 24

25 CoreLink CCN-504: Server Unit of Compute Slave interfaces from rest of SoC Sharing coherent view into compute unit s view of memory Single Inner-coherent Region (SMP) Quad Cortex-A57 Quad Cortex-A57 GIC-500 Quad Cortex-A57 Quad ACE Cortex-A GbE ACE DPI PCIe Crypto AHB DSP DSP DSP USB NIC-400 SATA L2 cache L2 cache L2 cache L2 cache MMU-500 CoreLink CCN-504 Cache Coherent Network 8/16MB L3 cache Snoop Filter Interface to Local DDR memory CoreLink DMC-520 x72 DDR CoreLink DMC-520 PHY x72 DDR Flash NIC-400 Network Interconnect GPIO Master interface to the rest of SoC and access remote memory 25

26 Local I/O and Remote Routing EUROSERVER Vision: Started 1 st Sept 13 Cortex-A15 Cluster CPU 0 CPU 2 L2 Cache CPU 1 CPU 3 Cache Coherent Interconnect (CCI-400) Cortex-A7 Cluster CPU 0 CPU 2 L2 Cache CPU 1 CPU 3 Mali T600 series GPU Shader Core 0 Shader Core 1 L2 Cache SMMU Shader Core 2 Shader Core 3 AMBA Extensions Interface (Master) AMBA Extensions Interface (Master) Debug & Trace CoreSight Resources Mgt System Power NIC 400 JTAG & Trace PMIC/ APB Bus 1) Start with a standard scalable compute unit DMC-400 LPDDR2/DDR3 Controller NIC 400 TrustZone enabled 2012 Compute Subsystem DDR PHY or DDR Memory On-Chip Memories (RAM, ROM) AMBA Extensions Interface (Slave) Base Peripheral 2) Connect a few together Compute Node Multi-Chip-Module along with its local memory partition Compute Chiplet Compute Chiplet Active Interposer (2D SoC + TSV) Bumps Package Substrate Memories 3) Put a few on a board using shared IO s Balls Non-Volatile Memory Configurable Multi-Protocol I/O Interfaces Consumer supply Compute Node (64xCPU) 256xCPU 4) In future, integrate Compute Node into a single MCM Compute Node Delivering a result 100x better than today Compute Node 26

27 27 Thank you