ARM Connected Community Technical Symposium Reaching High Performance System Design Using AMBA Fabric IP

Transcription

1 ARM Connected Community Technical Symposium Reaching High Performance System Design Using AMBA Fabric IP Tim Mace Senior Technical Marketing Manager Fabric IP BU, ARM 1

2 What is Fabric IP? Fabric IP is: Any IP component that moves or stores data but does not process it The central Fabric IP component is the on-chip bus but it also includes: Cache Controllers DMA Controllers Controllers Interrupt Controllers Management AMBA Designer Analyse the architecture Build the system AMBA Designer GIC Peripheral Peripheral Peripheral Peripheral Peripheral OptimoDE AR M CPU SMMU L2 Cache AMBA Interconnect System Cache DMA Dynamic Static Mem Mem Control Control 2

3 Fabric IP and System Performance All data traffic is transported through the Fabric IP Fabric IP cannot accelerate the system; it can only add latency Fabric IP is critical to system performance by: Minimising the additional latency Managing the additional latency to reduce system impact Over time, the role of Fabric IP in system performance is increasing: Bus masters (CPU, DSP etc.) are getting faster Dynamic memory initial access time is growing slowly Increased cycle latency System integration is enabling more bus masters per SoC Key system slaves are shared between masters System integration enables increased on-chip memory Caches and buffers increase the flexibility of the Fabric IP 3

4 System Bandwidth 1. Single, low-frequency master with a single-layer bus CPU contr oller The available bandwidth of the single layer interconnect is matched to t he bandwi dth requirements of the CPU No bandwidth limitations 2. Multiple, higher-frequency masters with a multi-layer bus CPU contr oller DSP DMA The peak bandwidth from t he 3 mast ers exceeds the capability of a single layer. Multi-layer increases the peak bandwidth to match. Bandwidth limitations in shared sl aves forces ar bitrati on adding latency The bus is more complex, limiting the maximum frequency but the masters are faster 3. Multiple, high-frequency masters with a multi-layer, pipelined bus + cache CPU DSP DMA Cache L2 Cache On-chip memor y in Cache significantly reduces the bandwidth to the memory controller contr oller Pipelined st ages in the interc onnect preser ve lat enc y but increase bandwidth with masters 4

5 AMBA Supporting the ARM Roadmap Investment in the ARM processor drives investment in the AMBA specification Release MHz (equiv alent Performance) Adv Development ARM926EJ-S ARM1136EJ-S AMBA ARM966E-S ARM1026EJ-S ARM946E-S ARM1176JZF-S ARM1156T2F-S MPCore AMBA 3 AXI Cortex-A8n Tiger OptimoDE Cortex-R4 Serval-E ARM7TD MI 100 Single Layer SC200 /SC210 SC100 /SC110 ARM968E-S Multi La yer Cortex-M3 Sandcat Worst case conditions 5

6 AMBA Cost AMBA is available with no Royalty payment minimising the costs of adoption. Substantial investment in AMBA from ARM driven by ARM CPU and partner s system requirements ensures that the specification continues to meet the customer requirements Performance AMBA 2 AMBA 3 APB provides a low complexity interface for register access. provides a low gate-count, high performance protocol. AXI adds advanced capabilities for pipelined, multi-threaded, multiple frequency domain systems. and AXI support single and multi-layer architectures Flexibility The widespread adoption of AMBA throughout the industry encourages the development of: Third party IP supporting AMBA A wide variety of thi rd party verifi cation tool s Support 6

7 AMBA 3 Interface Protocols AM BA 3 Pipelined, high-speed Bridges to AMBA 2 full Removed redundant features AMBA 3 APB Simple interface Low bandwidth, Low power Suitable for many peripherals Wait and error response AMBA 2 backward compatible AMBA 3 ATB Advanced Trace Bus System-wide debug and trace Shares resources AM BA 3 AXI High performance High speed Flexible Simple channel interface Burst based Multiple outstanding transactions Out of order data Simultaneous reads and writes Register Slice support Asynchronous interfacing Bridges to other protocols 7

8 Which AMBA Protocol? 1. Single,, low-frequency master with a single-layer bus CPU contr oller In this s ys tem, AMBA AH B is the opti mal protocol. It matc hes the capabilities of the CPU and easily meets the system speed requirements 2. Multiple,, higher-frequency masters with a multi-layer bus CPU DSP DMA With AMBA bas ed mast ers, t he AH B pr otoc ol f or t he i nt erconnec t matches. T he multi-layer archit ect ure provi des the bandwidth i n t he multi-master system. contr oller 3. Multiple, AXI, high-frequency masters with a multi-layer, pipelined bus + cache CPU Cache contr oller L2 Cache DSP DMA With AMBA AXI based pr ocess ors, the AXI i nt erconnec t matches t he CPU interface requirements. The multi-layer arc hitec ture provi des the high bandwidth r equired in the system. AM BA AXI pr ovides capabilities that allow: Pipelined int erconnect for high s yst em speeds and efficient frequenc y crossing Capabilities for optimising DMA and Dynamic memor y controller performanc e 8

9 AXI Channel architecture AXI interface implemented as five distinct channels W rite Address A0 A1 Write Data D00 D01 D02 D03 D10 D11 AXI Master W rite Response Read Address A2 A3 B0 B1 AXI Read D ata D30 D31 D20 D21 D22 D23 Data flows in a single direction in each channel Read and Write independent can occur in parallel Burst based: One address corresponds to multiple data items 9

10 AXI clock domain crossing Low latency Synchronous bridges: zero to <one slow clock cycle Asynchronous bridge: 3 or 4 receiving clock cycles Full bandwidth Valid sampled in fast clock domain Valid asserted in slow clock domain Theoretical minimum, due to double D-type synchronisers plus uncertainty 10

11 AXI built-in security support # 1 # 2 # 3 # 4 CPU Level 2 Cache AMBA AXI Interconnect DDR Controller TrustZone security as standard: APROT[0] privileged/normal APROT[1] Non-secure/secure APROT[2] Instruction/data APB Bridge # 5 # 6 Secure slave disappears from the memory map during non-secure accesses 11

12 AXI built-in cache support # 1 # 2 # 3 # 4 CPU Level 2 Cache AMBA AXI Interconnect DDR Controller The ACACHE[3:0] lines provide support for system level cache by providing the bufferable, cacheable and allocate attributes APB Bridge # 5 # 6 12

13 Fabric IP for CPU 2 channel 8 channel DMAC DMAC ARM7 ARM9 PL08 1 PL08 0 LCD Ctrl PL11 1 Downsizer Arbiter Decoder VIC PL19 0 PL19 2 BusMatrix SRAM / DR AM Ctrl PL24 2 PL24 3 PL24 4 PL24 5 SRAM Ctrl PL24 1 Stick HC PL20 0 to APB EBI PL22 0 Remap WDog Timers UART PL01 1 SPI PL02 2 PS/2 PL05 0 GP I/O PL06 1 Current New pr oducts ADK Com ponents 13

14 Controller Product Range PL24x Ctrl Ctrl DDR SDRAM NAND SRAM/ NOR SRAM NAND Engineering Base library Data Ports Static Su pport Dyn amic M emory Support PL241 Ctrl SRAM/ NOR 1 32-bit Syn c/async NOR Flash Async SR AM Cellul arr AM (1. 0, 1. 5, 2. 0) OneNAND PL242 Ctrl NAND SDRAM 4 16-bit N AND Fl ash 32-bit SDRAM PL243 Ctrl SRAM/ NOR SDRAM 4 32-bit Syn c/async NOR Flash Async SR AM Cellul arr AM (1. 0, 1. 5, 2. 0) OneNAND 32-bit SDRAM PL244 Ctrl NAND DDR 6 16-bit N AND Fl ash 16-bit DDR SDRAM PL245 Ctrl SRAM/ NOR DDR 6 32-bit Syn c/async NOR Flash Async SR AM Cellul arr AM (1. 0, 1. 5, 2. 0) OneNAND 16-bit DDR SDRAM 14

15 PL24n Functional Block Diagram Refresh Counter Reg Bloc k Manager Manager Formatting Arb Mux Relinking Open Row Scheduler Cache Arbitrati on Queue Ex-Ac Monitors Command Formatter Command W data Data Timer Post Delay Pipe EB I Bank Bank Bank Bank Power Down Pre Delay Pipe Data Ctrl Dynamic Pad I/F R Data clock domain Manager Command Formatter EBI I/F Command W data R Data clock domain I/F Static Pad I/F 15

16 PL24n PHY Integration Command EB I Power Down Clock enable Internal Clock Pad I/F Master DLL PHY Mem clock Command W data Data Timer Post Delay Pipe Bank Data Bank Bank Ctrl Bank Pre Delay Pipe Command Internal Clockn DQS Internal 2xclock DQ Internal 2xclockn D Q D Q D Q DQS out DQ out DQ in R Data Sync Data Internal Clock Q D DLL DQS in 16

17 PL24n PHY Integration PHY PLL Command EB I Power Down Clock enable Internal Clock Pad I/F DLL Delay Code W data Data Timer Post Delay Pipe Bank Data Bank Bank Ctrl Bank Pre Delay Pipe Command Internal Clockn DQS Internal 2xclock DQ Internal 2xclockn D Q D Q D Q R Data Sync Data Internal Clock Q D Delay 17

18 PHY Product Solutions DDR I SDRAM 130nm 533MHz PLL 800Mbs DLL 2.5V Up to 400Mb/s 90nm 533MHz PLL 800Mbs DLL DDR 1/2 DDR1/2/ Mobile DDR DDR II 1.8V Up to 800Mb/s SDRAM/ RLDRAM 130nm 90nm 533MHz PLL 533MHz PLL 800Mbs DLL 800Mbs DLL DDR 1/2 DDR 1/2 GDDR III 1.8V Up to 1.6Gb/s SDRAM/ RLDRAM 130nm 90nm 800MHz PLL 800MHz PLL I/O Placement Flexibility No hardened PHY Problem of the chip corner Variability of bump requirements Match supply / decap pad frequency to actual needs (varies widely with package type) 1600Mbs DLL 1600Mbs DLL GDDR3 DDR1/2/GDDR3 Power group IO group 18

19 Fabric IP for AXI Type Interconnect Static Controllers Dynamic Controllers DMA Controllers Interrupt Controllers Part PL301 PL351 PL352 PL353 PL354 PL340 PL341 PL330 PL390 Description Full support for AMBA protocols, multiple archietctures NAND Flash memory controller SRAM, PSRAM and NOR Flash memory controller NAND + SRAM/PSRAM/NOR Flash memory controller Dual SRAM/PSRAM/NOR Flash memory controller SDRAM/DDR/Mobile-DDR memory controller DDR2 memory controller Highly flexible, micro programmed DMA architecture Highly flexible DMA controller with support for MP and TZ In development In development In development Highly configurable Support a wide range of system architectures whilst minimizing overheads Business models to support configurability Tuned for AXI interface performance & interaction with interconnect fabric Integrated with AMBA Designer for configuration and RTL generation Standalone operation also supported Modelling First development methodology 19

20 AMBA Designer An integrated graphical tool that allows users to: Construct & Configure Simulate Analyze.complex AXI-based fabric interconnect and sub-systems RTL Implementation IP through PL301 Engine 20