INTRODUCTION. icegate

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1 Using icegate in Ultra Low Power ice FPGA INTRODUCTION In today s handheld and portable applications market, power price and space form the crux of the competition, especially with FPGAs and CPLDs playing an increasingly important role in meeting market demands of convergence, innovation, and time to market. This application note discusses a creative technology that reduces static power consumption to even lower levels that were previously thought unreachable. Static power is based on the current that is drawn by the FPGA when it is powered up, configured, and doing no work. Deep within the FPGA, transistors leak current even when they are not switching. Leakage varies from one process to another, depending on the oxide layer thickness. This form of static current is what most FPGA vendors declare in their technical documentation. Practically however, true static power is seldom reachable in a design where I/Os are toggling and inputs are switching even when the FPGA is in standby mode or simply doing no work. What most FPGA vendors declare as their static/standby low power is unrealistic and cannot be reached in any design example, where typically, inputs are switching and I/Os are toggling. What Silicon Blue offers is a creative methodology to overcome this problem by blocking unwanted inputs and thus reducing power consumption to the definitive static power where only the fabric is powered on but no I/O is contributing to final power consumption. icegate is a programmable ON/OFF switch that eliminates unnecessary toggling of inputs when these are not in use. icegate In a typical CPLD/FPGA design, external logic is needed to block switching inputs, thus raising system power and cost. True static power cannot be practically achieved unless inputs are being blocked by a certain mechanism. No design can operate with zero inputs toggling. icegate allows true static power to happen without using any external resources. icegate is implemented in two stages. The first stage consists of a Bank Latch Enable control signal (icegate HOLD) that propagates throughout all pre IO cells pertaining to one bank. The control signal optionally enables asynchronous inputs within a bank and saves power by selectively inhibiting switching of input signals during low power operation. A second stage consisting of configuration bits that control each individual pin s participation in icegate. 1

2 Individual pins within the I/O bank can bypass the Input Enable control and feed directly into the Programmable Interconnect, remaining active during low power operation. icegate circuitry is implemented in an interface cell between the logic core and the I/O cell that is called the PRE IO cell. The figure below shows PRE IO Cell architecture and icegate implementation. PRE-IO CELL LOGIC CORE Input Clock icegate HOLD cbit[1] cbit[0] Figure 1: Pre IO Cell Architecture The following table shows the inputs, outputs, and controls pertaining to the icegate design in the PRE IO cell: Table 1: Pre IO Cell Signal Description Signal Input Clock icegate HOLD cbit[1:0] Description Enables the two registers D0 and D1 Bank enable signal Configuration bits for individual pin control icegate_hold signal is shared among all I/Os placed in the same bank. Such architecture gives icegate an inherent advantage over other architectures by competitors where input blocking is implemented via a rail that affects all banks and all I/Os at once. 2

3 Using icegate to Achieve Ultra Low Power We design a sample application where the chip is filled with 88 loadable counters. We run the code from two different clock sources: 32 MHz oscillator, and 32 khz oscillator. Both inputs are sourced through global buffer inputs. The output of the global buffer connects to the CLK input of the Programmable Logic Block in use. The CLK signal is shared among all flip flops in a programmable logic block. Thus, a clock source can be actively drawing power by propagating throughout the FPGA fabric even when not being used. The following figure shows the MUX implementation in an ice04 FPGA. Figure 2: Clock MUX architecture in an ice04 FPGA 3

4 Table below describes the settings required for enabling icegate: Table 2: Two icegate configurations for 32 MHz input CLK_SELECT LATCH_32MHz icegate 0 1 ENABLED 0 0 DISABLED 1 0 DISABLED We measure the internal power consumption on the ice04 device before we enable icegate on the 32 MHz input and the current draw is ma at 1.2V which is equivalent to 1.31 mw. When we do enable icegate, the current draw is 51 ua at 1.2V which is equivalent to 61 uw: that is 95% power reduction! The table below shows the various power consumption numbers depending on icegate. Table 3: Static Power Consumption with icegate System Mode Description Low Speed Operation (32kHz) Low Speed Operation (32kHz) icegate Enabled Yes No Power Consumption 61 uw 1.31 mw 4

5 Figure 1 below shows the evaluation board setup with ammeter measuring ma. Figure 3: Ammeter reading of ma before enabling icegate Figure 2 shows the current dropping to 51 ua after enabling icegate. Figure 4: Ammeter reading of 51uA after enabling icegate 5

6 Configuring icegate Every pin can be individually configured whether to use icegate latch enable or not. The following is an input pin function truth table that shows the functional description based on the pin type bit assignment. The designer must then set the pin type in HDL code to participate in icegate and the input to be blocked appropriately. The following table shows the two configuration bits PIN_TYPE associated with each individual pin. Table 4: Input Pin Function Truth Table # Parameter Name Mnemonic PIN_TYPE[1:0] Functional Description of Package Pin Input Operation 1 PIN_INPUT 0 1 Simple input pin 2 PIN_INPUT_LATCH 1 1 Disables internal data changes on the physical input pin by latching the value. 3 PIN_INPUT_REGISTERED 0 0 Input data is registered in input cell 4 PIN_INPUT_REGISTERED_LATCH 1 0 Disables internal data changes on the physical input pin by latching the value on the input register Designers must follow the three simple guidelines in implementing icegate: 1. If IO cell does not use the Latch function: leave LATCH_INPUT_VALUE (icegate enable) unconnected and set PIN_TYPE[1] = 0; 2. If IO cell uses the Latch function: connect LATCH_INPUT_VALUE (icegate enable) to the control signal and set PIN_TYPE[1] = 1; 3. It is a legal placement if all IOs assigned to the same bank where all IOs with PIN_TYPE[1]=1 have the same LATCH_INPUT_VALUE, and the rest of the IOs with PIN_TYPE[1]=0. The designer implements icegate in HDL code. The following code snippets demonstrate how we implemented icegate functionality on the 32 MHz oscillator input. First, the bank latch enable is defined as indicated in red in the following code: 6

7 Component SB_IO is GENERIC ( PIN_TYPE: STD_LOGIC_VECTOR (5 downto 0)); Port ( PACKAGE_PIN: in_std_logic; LATCH_IPUT_VALUE : in STD_LOGIC; D_IN_0 : out STD_LOGIC ); end component; The code below shows the IO cell configuration and the mapping of the Bank Latch Enable signal (LATCH_INPUT_VALUE) to the 32 MHz clock enable input signal. CLK32MHz_Buffer: SB_IO generic map ( PIN_TYPE => ) Port map ( PACKAGE_PIN => CLK_32MHz, LATCH_INPUT_VALUE => LATCH_32MHz, D_I_0 => CLK_32MHz_GB ); Consecutively, the Bank Latch Enable is negated and connected to the clock select of the clock mux. When the select signal of the clock mux is zero the 32 khz input is active, which means that the 32 MHz input must be latched so icegate is enabled. LATCH_32MHZ <= not (CLK_SELECT) icegate vs. Low Power Mode Low power modes or sleep modes are prevalent in today s low power integrated circuits. While these modes do present numerous benefits for the designer, they lack significantly behind what the icegate technology can offer in terms of power savings. What makes icegate so powerful and attractive is the ability to select individual pins while keeping the device operational and logic available for the rest of the chip. Such features are not permissible in low power mode schemes. 7

8 SUMMARY Portable Applications are particularly sensitive because they draw a lot of battery power. A new methodology to reduce static or dynamic power consumption can be very effective in improving battery life. icegate was designed to stop unwanted input switching from continuously draining power and that can lead to nearly 95% decrease in power consumption. With power saving techniques such as icegate, ice FPGAs allow designers to build full custom designs easily meeting targets for system cost and power. 8