Presentation Outline Overview of FPGA Architectures Virtex-4 & Virtex-5 Overview of BIST for FPGAs BIST Configuration Generation Output Response Analy

Transcription

1 PRODUCTION SYSTEM-LEVELEVEL USE OF BUILT-IN SELF-TESTEST FOR IRTEX-4 4 & VIRTEX VIRTEX 5 FPGAS IRTEX-5 FPGA Chuck Stroud, Brad Dutton, Mary Pulukuri, Brooks Garrison, and Yao Jia (the BIST Dudes & Dudettes)

2 Presentation Outline Overview of FPGA Architectures Virtex-4 & Virtex-5 Overview of BIST for FPGAs BIST Configuration Generation Output Response Analyzers BIST Results Retrieval Test Time Analysis Modification for System-Test Pins BIST Approaches for: CLBs & IOBs Brad Dutton DSPs Mary Pulukuri BRAMs Brooks Garrison

3 FPGA Architectures Configurable logic blocks (CLBs) Programmable I/O blocks (IOBs) Specialize Cores RAMs, DSPs, Processors Programmable interconnect network up Configuration memory RAM Typical FPGA Resources Small FPGA Large FPGA Logic CLBs per FPGA ,920 LUTs and flip-flops flops per CLB 1 8 Routing Wire segments per CLB PIPs per CLB 139 3,462 Bits per memory core ,432 Special Memory cores per FPGA Cores DSP cores Other Input/output cells 62 1,200 up

4 Architecture for Virtex-4 LX15 IOBs RAMs DSPs center column IOBs DCMs BUFGs BSCAN RAMs RAMs IOBs CLBs all CLBs include 2 SliceM (lower slices) and 2 SliceL (upper slices) each slices has 2 4-input LUTs and 2 FFs SliceM LUTs can also function as 16-bit RAMs and shift registers

5 Virtex Virtex-4 Devices & Architectures 4 Devices & Architectures Rows Rows Rows Rows part part Rows Rows Rows Rows part part PowerPC locations PowerPC locations PowerPC locations

6 Architecture for Virtex-5 LX30 IOBs Center column: IOBs DCMs RAMs DSPs BUFGs RAMs BSCAN CLBs SliceL all CLBs include 2 slices each slice has 4 6-input LUTs and 4 FFs IOBs SliceM bottom slice is SliceM and top slice is SliceL in CLB alternating columns of SliceMs Exception: column left of DSPs SliceM LUTs can also function as 64-bit RAMs and 32-bitshift registers

7 Virtex-5 Architectures Similar architecture, frame structure and order I/O cells not along outside column on right side Center column (Xs) not in center of array More columns to right side of center EMAC, PCI, and GBTs in 2 right columns LXT, SXT, and FXT devices Not in LX devices New V5s: LX20T & LX/LXT155 FXT devices w/ppcs part Rows LX & LXT Legend O 4 R 2 D 8 X 8 R 4 O 4 T C #=#CLBcols O 4 R 2 D 8 X 8 R 4 O 4 T C D=DSPs O 4 R10R 2 D 8 X 12R10 10 R 4 O 4 T C R=RAMs O 4 R10R 2 D 8 X 12R10 10 R 4 O 4 T C O=I/O cells O 4 R22 R 2 D 2 D 2 R20 X 20R 6 R 22 R 4 O 4 T C X=IO&DCM O 4 R22 R 2 D 2 D 2 R20 X 20R 6 R 22 R 4 O 4 T C T/C=T only SXT O 4 R 2 D 2 D 2 R 2 D 2 D 2 R 2 X 2 R 2 D 2 D 2 R 4 O 4 T C O 4 R 2 D 2 D 2 R 2 D 2 D 2 R 2 X 2 R 2 D 2 D 2 R 4 O 4 T C

8 BIST for FPGAs Basic idea: reprogram FPGA to test itself No area overhead or performance penalties Applicable to all levels of testing Cost: Application independent testing Memory to store BIST configurations Goal: minimize number of configurations Test time = download + execute + results Dominated by download time Goal: minimize downloads and/or download time Results retrieval is second most impact Goal: provide Pass/Fail indication (fault detection only fault detection only)

9 AUBIST Approach Configure some logic resources to act as Test Pattern Generators (TPGs) Output Response Analyzers (ORAs) Configure other resources to be tested Wires Under Test (WUTs) Blocks Under Test (BUTs) We do not assume any fault-free free resources!! multiple BIST configs test all modes of operation For all configurations, we maintain constant placement of TPGs, ORAs, & BUTs routing of TPG-to to-but & BUT-to to-ora minimizes download time via partial reconfiguration Automatic generation of BIST configurations

10 Automated BIST Generation Process C C programs generate.xdl files TPGs, ORAs, BUTs, routing VHDL & synthesis do not allow control of test conditions.xdl to.ncd xdl xdl2ncd bist.ncd FPGA Editor Design Rule Check Route design.ncd to.xdl Modification programs generate remaining BIST configurations for BUTs.NCD to.bit BIST Programs XDL file XDL.exe NCD file BitGen.exe BIT file download FPGA Editor

11 Automated BIST Generation Example User specifies any portion of array to test Start row & column End row & column TPGs, ORAs, and BUTs instantiated & located based on rows XDL is not routed FPGA Editor used for routing with no pin swap PAR used when pin swap is allowable Programs modify routed XDL for subsequent BIST configurations Virtex-4 FX20 PowerPC LUT RAMs Under Test TPGs (DSPs & Block RAMs)

12 FPGA BIST Architecture Multiple TPGs supply patterns to alternating rows/columns of BUTs TPGs constructed from Configurable Logic Blocks, or Other embedded cores =TPG =BUT =ORA DSPs (accumulating prime constant) Or DSPs & Block RAMs DSP counter addresses RAM (ROM) RAM (ROM) stores test patterns ORAs compare output responses of identically configured BUTs Circular comparison of BUTs Provides good fault detection Can identify multiple faulty BUTs with

13 Review of ORA Designs ORAs have big impact on BIST architecture Bigger impact than TPGs Need to retrieve BIST results from ORAs Iterative ORA All ORAs in row/column fed to 1 IO pin Poor diagnostic resolution Integrated ORA/scan chain Higher diagnostic resolution More logic for scan chain Interface to Boundary Scan Configuration memory readback No logic for scan chain Partial configuration memory readback Readback from embedded processor Ts s from BUT Outputs Outputs Outputs from adja fr acent from BUTs Shift In Shift LUT LUT LUT LUT LUT Iterative OR-chain = single pass/fail for 103,680 ORAs Pass/Fail

14 New ORA Implementation Old comparison-based ORA BUT i output k BUT j output k Logic 1 latched in FF due to mismatches LUT Configuration memory readback used to get results CLBs have dedicated carry chain for fast adders 01TDI and counters O O O New ORA latches logic 0 due to mismatch Carry chain performs iterative OR function Single pass/fail bit Expected failures require clock enable BUT i output k BUT j output k Clock enable LUT init 1 Only read configuration memory to get failing ORA init 0 TDO 1=pass 0=pass 0=fail 1=fail carry-out carry-in

15 V4 BIST Download Time Test time dominated by time to download BIST This data for set of 221 BIST configurations Downlo oad time Sec conds Full Configuration Full+Partial Reconfig Compressed+Partial Reconfig

16 V4 BIST Results Retrieval Time Partial configuration memory readback of ORAs Results re etrieval tim me Seconds After Every Configuration After Every Test Session Some loss of diagnostic resolution

17 V4 BIST Total Test Time Execution of BIST sequence is negligible Total test time Seconds BIST Sequence Configuration Download Results Retrieval 3

18 Improving Test Time & Access Previous data for Boundary Scan interface Maximum TCK frequency = 50MHz SelectMap (slave parallel) interface 32-bit interface = 32x speed-up 100MHz operation = 2x speed-up Need to provide access for 4-8 pins Company using BIST configs does not have system-level access to Boundary Scan interface BIST clock input (free running system clock) Test Data Out (OR-chain output) 0 1 Test Data In (OR-chain input) Synchronized Reset to TPGs 1 carry-out LUT carry-in Avoid glitches on pass/fail due to 250 picosec delay in ORAs Use 2 synchronizing FFs in ILOGIC module of Reset pad Some BIST approaches have added test mode controls System-test test pins option added to BIST programs

19 V5 & V4 Configurable Logic Blocks (CLBs) CLB is most abundant logic resource Switch Matrix 25,920 CLBs in largest Virtex-5 Note: Virtex 207,360 FFs and 6-input LUTs Note: Virtex-4 CLBs include 4 Slices with 2 FFs and 2 4-input LUTs each ~650 configuration bits per CLB Some CLBs include SliceMs (LUT RAMs) SliceM can form small RAMs or Shift Register COUT CLB SLICE0 (SliceM) COUT SLICE1 (SliceL) 6 LUT/ RAM (64-bit) Carry Logic FF/ Latch

20 V5 & V4 SliceL BIST Architecture DSP accumulator TPG, 12 outputs Accumulate prime number 0xCA6691 (Gupta, Rajski & Tyszer CCAD 94) Iterative-OR ORA Row based circular comparison 4096 BIST Clock Cycles per phase Two multiple phase test sessions: east and west TPG TPG East TPG TPG West

21 V5 & V4 SliceM BIST Architecture Block RAM TPGs store RAM test vectors March Y + Dual-port March (A. van de Goor) 2048 x 18-bit BRAM, 8N = 8*256 = 2048 vectors Iterative-OR ORA Column based circular comparison One multiple phase test session for all SliceMs Every CLB with a SLICEM has a SLICEL for ORA TPG TPG BUT ORA TPG 2048 BIST Clock Cycles per phase

22 # Faults Dete ected V-5 SliceL BIST Fault Coverage Single Stuck-at Simulation Individual FC Cumulative FC Gate Configuration # Gate-level model (AUSIM) Fault Injection Individual FC 70 Cumulative FC # Faults Dete ected Configuration # 3007 gate-level collapsed stuck-at faults 100% cumulative coverage in 6 phases w/ DSP TPG Configuration memory fault injection 614 configuration bit stuck-at faults

23 # Faults Dete ected V5 SliceM BIST Fault Coverage Single Stuck-at Simulation Individual FC 5000 Cumulative FC Configuration # Gate Gate-level model (AUSIM) # Faults Dete ected Fault Injection Individual FC 60 Cumulative FC Configuration # 8462 gate-level collapsed stuck-at faults 100% cumulative coverage in 5 phases w/ RAM tests Configuration memory fault injection 85 configuration bit stuck-at faults

24 V4 & V5 CLB BIST Programs Two XDL template file generation programs V5plbbist SliceL BIST template (east & west) V5lrambist SliceM BIST template Two XDL modification programs V5plbmod Modifies SliceL template to 6 phases V5lrammod Modifies SliceM template to 5 phases System System-level test pins interface I/O buffers and ILOGIC for TPG reset, test clock, test in, and test out included in template at user s request Placed at bonded I/O site by user in FPGA Editor Boundary Scan interface is also supported Provides device & package independent interface

25 Virtex-5 CLB BIST Summary Total Config. Max. BIST BIST Boundary Scan SelectMAP Device Size (kb) Clock Freq. CCs test time test time LX20T 1, MHz 59, ms 5.89 ms LX30T 2, MHz 59, ms 8.06 ms LX50T 3, MHz 59, ms ms LX85T 6, MHz 59, ms ms SX35T 3, MHz 59, ms 9.93 ms SX50T 5, MHz 59, ms ms SX95T 8, MHz 59, ms ms 17 total configurations achieve 100% single S.A. fault coverage in every CLB Downloads: 3 compressed-full 15 and 12 partial reconfigurations 10 Worst Case: Boundary Scan (50 5 MHz) Tim me (ms) Readback Execution Configuration

26 V5 & V4 I/O Tile BIST Two I/O Cells (master and slave) form an I/O Tile Dedicated shift routing for SERDES data width expansion Routing to support complementary differential I/O standards Our Approach: Test I/O Logic and I/O SerDes modes separately To/from Device Resources From Device Resources To/From Device Resources From Device Resources Input Logic (ILOGIC) Output Logic (OLOGIC) Input Logic (ILOGIC) Output Logic (OLOGIC) Master I/O Cell BSCAN Access

27 V5 & V4 I/O Tile BIST Previous Approach: : Use Bi- directional I/O Buffers Limits in-system applications Must tri-state connecting devices Passive components (e.g. LEDs) can cause false failures at high frequency (Lerner, Vemula & Stroud NATW 06) Alternative Approach (Virtex- 4 & Virtex-5): Use feedback routing to bypass I/O Buffers I/O Buffers tested separately Wafer and device-level tests Simple test for I/O buffers: 2-bit counter, min. 5 clock cycles To/from Device Resources From Device Resources To/From Device Resources From Device Resources Input Logic (ILOGIC) Output Logic (OLOGIC) Input Logic (ILOGIC) Output Logic (OLOGIC) Master I/O Cell

28 V5 & V4 I/O Tile BIST Architecture Block RAMs for TPGs store modified pseudorandom test patterns Logic: 2048 x 18-bit SerDes (more inputs): 1012 x 32-bit Iterative-OR ORA Column based circular comparison TPG TPG BUT ORA TPG 2048 BIST clock cycles for I/O Logic phases, 1012 BIST clock cycles for I/O SerDes phases

29 V4 & V5 I/O Tile BIST Programs Three XDL template file generation programs V4iobist I/O logic resources V4iobistios I/O SerDes logic resources V4iostd all bi-directional I/O standards Three XDL modification programs V4iobmod I/O Logic resources V4iobmodios I/O SerDes resources V4iobrmod all bi-directional I/O standards System-level test pins interface System-level test pins create un-testable I/O Cells User provides pin names for test pins prior to BIST template generation I/O Buffers and ILOGIC for pins interface placed automatically by template generation programs Boundary Scan also supported Package & device independent interface to BIST

30 All I/O Cells Under Test in Virtex-5 LX30T as viewed in Xilinx FPGA Editor Block RAMs for TPG DSPs for TPG I/O Tiles under test & ORAs Implemented in all Virtex-4 & Virtex-5 devices Virtex Virtex-5 configs. 6 6 I/O Logic 9 9 I/O SerDes 68 I/O Standards Virtex-4 configs. 5 5 I/O Logic 9 9 I/O SerDes 68 I/O Standards

31 All I/O Cells Under Test in Virtex-5 LX30T as viewed in Xilinx FPGA Editor Block RAMs for TPG DSPs for TPG I/O Tiles under test & ORAs Implemented in all Virtex-4 & Virtex-5 devices Virtex Virtex-5 configs. 6 6 I/O Logic 9 9 I/O SerDes 68 I/O Standards Virtex-4 configs. 5 5 I/O Logic 9 9 I/O SerDes 68 I/O Standards

32 All I/O Cells Under Test in Virtex-4 FX12 as viewed in Xilinx FPGA Editor Block RAMs for TPG DSPs for TPG Power PC I/O Tiles under test and ORAs Implemented in all Virtex-4 & Virtex-5 devices Virtex Virtex-5 configs. 6 6 I/O Logic 9 9 I/O SerDes 68 I/O Standards Virtex-4 configs. 5 5 I/O Logic 9 9 I/O SerDes 68 I/O Standards

33 Virtex-4 DSP Architecture 2 2 DSP slices per tile tiles in 1-8 columns Each DSP includes: 3-input, 48-bit adder/subtractor P P = Z±(X+Y+Cin X+Y+Cin) Optional accum reg C (48) 18x18-bit 2's-comp multiplier (w/o adder) User controlled operational modes For X, Y, & Z MUXs Configuration bits control other MUXs Pipelining registers A(18) B(18) A(18) B(18) Outputs w/ dedicated routing X Y Z Inputs for cascading Outputs w/ dedicated routing X Y Z ± ± P (48) P (48)

34 DSP BIST Architecture 2 2 TPGs drive alternate rows of DSPs tiles Prevents faulty TPG from escaping detection TPG drives both DSPs in tile Needed for cascade tests DSPs driven by different TPGs compared by ORAs Like DSPs compared Slice 0 compared to slice 0 Slice 1 compared to slice 1 Top DSPs compared to bottom DSPs in column based circular comparison ORAs for bottom DSPs are BSCAN shift reg test mode TPG 1 TPG 0 DSP s1 DSP s0 DSP s1 DSP s0 DSP s1 DSP s0 DSP s1 DSP s0 DSP s1 DSP s0 DSP s1 DSP s0 ORAs ORAs ORAs ORAs ORAs ORAs ORAs ORAs ORAs ORAs ORAs ORAs

35 DSP BIST Configurations 5 5 downloads to FPGA 1 1 compressed download (<50% of full config) 4 4 partial reconfigurations (<0.5% of full config) only change DSP configuration bits 7 7 BIST sequences # Fault ts Detected 2 2 BIST configurations are run twice different test mode input values for multiplier/adder test algorithms Individual FC Cumulative FC Fault coverage = 97.4% Currently investigating undetected faults

36 Max Clock Fre eq (MHz) Max Clock Freq (MHz) lx lx25 lx40 lx60 DSP BIST Timing Analysis lx80 lx100 lx160 lx200 fx12 fx20 Virtex-4 FPGA Bottom BIST Bottom TPG Bottom BIST Middle TPG fx40 fx60 Bottom Middle fx100 fx140 sx25 Top BIST Bottom TPG Top BIST Middle TPG sx35 sx55 Goal: f clk 50MHz TPG position affects timing Best results with TPG in middle Largest devices f clk 50 MHz Run BIST on half of array & reposition TPG Doubles # BIST

37 DSP BIST in FPGA Editor V4 SX35 V4 FX12 V4 LX160 V5 LX30 Routed Routed Unrouted Unrouted

38 DSP BIST Generation Programs Virtex-4 V4DSPBIST program for XDL template generation V4DSPMOD program for XDL template modification for 5 BIST configurations 2 2 interfaces for BIST inputs and output: TPG reset, TPG clock, Test Data In, Test Data Out, plus 3 test mode inputs Virtex Virtex-5 Boundary scan interface Shift register shifts control inputs into TPGs System pins interface 7 BIST I/O connect to user specified pins V5DSPBIST program currently under development for XDL template generation

39 Virtex-4 Block RAM (BRAM) BIST BRAM BRAM Power PC BRAM BRAM BRAM BRAM BRAM BRAM 32-bit Address ADDRA ADDRB 32-bit I/O Ports + 4 Parity Bits Input: DIA, DIB Output: DOA + DOPA, DOB + DOPB 4 Operation Modes BRAM (regular) FIFO Cascade ECC

40 V4 BRAM BIST BRAM MarchLR tests for single port faults 2 BIST Configurations March s2pf & d2pf tests dual port faults 1 BIST Configuration MATS+ tests programmable address/data widths 3 BIST Configurations FIFO 2K, 512, 1K tests the FULL and EMPTY flags 3 BIST Configurations 4k tests programmable ALMOSTFULL/EMPTY flags 12 BIST Configurations (may reduce to 2 with some fault detection loss) ECC WREN, RDEN tests Hamming bit encode/decode logic 2 BIST Configurations Cascade UPPER, LOWER tests upper/lower RAM cascading 2 BIST Configurations

41 BRAM BIST Layout Block RAMs - Green ORAs Blue TPGs TPG0 red TPG1 yellow Unrouted BIST Routed BIST

42 BRAM BIST Programs V4 BRAM BIST Condensed 12 programs down to 2 V4RAMBIST generates BIST template file for specified device and BIST type (BRAM, FIFO, ECC, Cascade) V4RAMMOD modifies routed XDL for Block RAMs to subsequent BIST configuration(s) BIST Additions Under Development Iterative ORA-chain Gives user a single PASS/FAIL signal System-test test pins option Gives user BIST control access if desired or

43 Virtex-4 Routing Resources Double Lines (per switch box) pass by 2 CLBs N/S/E/W 10 wires for each direction, 3 terminals Hex lines (per switch box) pass by 6 CLBs N/S/E/W 10 wires for each direction, 3 terminals Long lines (per switch box) pass by 24 CLBs Bi-directional i+6 i+2 i+24 i+5 i+1 i+18 i+4 i i+12 i+3 i+2 i+6 i+1 i

44 Virtex-4 Routing Resources Terminals BEG Long lines N/S 2 BEG 0-9 Switch Box N/S 2 MID 0-9 N/S 2 END 0-9 slices MID END PIPs 3,312 PIPs per switch box Non-CLB columns have same

45 Cross-Coupled Coupled Parity Approach ORA (Oo) odd parity ORA even parity ORA (Oe) even parity ORA odd parity Slice 3 Slice 1 Podd Cu1 Cu0 Peven Cd1 Cd0 G LUT G LUT Podd Pass /Fail Pass /Fail Test Pattern Sequence Cu 1 Cu 0 Po Cd 1 Cd 0 Pe TPG (To) count-down odd parity TPG (Te) count-upup even parity Slice 2 Slice 0 G LUT F LUT Cd1 Cd0 G LUT Peven Cu1 Cu0

46 Global Routing BIST Configurations Routing Resource Direction N S E W Total Configs CLB double lines Non-CLB column double lines 4 4 9* CLB hex lines Non-CLB column hex lines 2 2 5* CLB long lines Non-CLB column long lines Total BIST Configurations 44 * 1 extra BIST configuration due to missing connections in non-clb columns

47 Actual Implementation Results ORA with iterative OR-chain remains an open problem in routing BIST due to required ORA /TPG positions and routing congestion

48 Summary Opportunity to put work into production Overcome problem of non-boundary Scan access Developed a new ORA with iterative-or chain Provides single Pass/Fail indication No configuration memory readback needed Only used by applications that want diagnosis Result is a significant reduction in test time Production grade software additional effort Provided a useful and unique learning experience for students working on project