A2090A HARD DISK CONTROLLER TECH DATA. Commodore Business Machines, Inc Wilson Drive, West Chester, Pennsylvania U.S.A.

Transcription

1

2 E22/3-4.2 A2090A HARD DISK CONTROLLER TECH DATA OCTOBER, 988 PN Commodore Busiess Machies, Ic. 2 Wilso Drive, West Chester, Pesylvaia 9380 U.S.A. Commodore makes o expressed or implied war raties with regard to the iformatio cotaied herei. The iformatio is made available solely o a as is basis, ad the etire risk as to quality ad accuracy is with the user. Commodore shall ot be liable for ay cosequetial or icidetal damages i coectio with the use of the iformatio co taied herei. The listig of ay available replace met part herei does ot costitute i ay case a recommedatio, warraty or guaraty as to quality or suitability of such replacemet part. Reproductio or use without expressed permissio, of editorial or pictorial cotet, i ay matter is prohibited. This maual cotais copyrighted ad proprietary iformatio. No part of this publicatio may be reproduced, stored i a retrieval system, or trasmitted i ay form or by ay meas, electroic, mechaical, photocopyig, recordig or otherwise, without the prior writte permis sio of Commodore Electroics Limited. Copyright 988 by Commodore Electroics Limited. All rights reserved.

3 A2090A HARD DISK CONTROLLER TABLE OF CONTENTS ri TITLE PAGE DESCRIPTION! I SPECIFICATIONS " FUNCTIONAL DESCRIPTION 3 H I/O DEFINITIONS 5 HOST INTERFACE PROTOCOL 6 r-i COMMANDS 9 USER MANUAL ADDENDUM 7 I! MAJOR PARTS LIST 2 ~] COMPONENT PARTS LIST 2 PCB LAYOUT 22 SCHEMATICS #3980 REV. A 23 H

4 A2090A HARD DISK CONTROLLER Amiga Hard Disk/SCSI Cotroller (A2090A) Techical Referece Maual.0 Descriptio The Amiga Hard Disk/SCSI Cotroller is a itelliget high performace cotroller desiged to iterface both ST506 hard disk drives ad SCSI devices to the Amiga expasio bus architecture. A backgroud commad processor provides high level commad iterpretatio miimizig Host itervetio. Data is trasferred to ad from the Host via DMA (direct memory access) with FIFO allowig high data throughput while maitaiig reasoable bus badwidth for other bus cotrollers.. Features Auto-boot from hard disk devices Support for up to two ST506 hard disk drives Full SCSI with Macitosh Plus compatibility High level commad iterpretatio ad exceptioal hadlig performed by Z80 processor Support for up to 8 heads, 2048 cylider with 52 bytes/sector Idividually Programmable Drive Characteristics : sector iterleave 32 bit ECC for data correctio Multiple block trasfers Full auto-cofig compatibility Real time data trasfer rates of up to 8s/byte via DMA 2.0 Specificatios 2. Performace Hard Disk (ST506) SCSI Host Ecodig method: Cylider per head: Sectors per track: Sector legth: Heads: Drive Selects: Step Rate: Data Trasfer Rate: Write Precomp Time: Sector Iterleave: Sector Iterleave Across Heads: Ecc Polyomial: Burst Error Correctio: ANSI X3T9.2 compatible MFM Up to 2048 Up to us to 6.5 ms 5.0 Mbit/sec. 2 aosec. : :2 32 bits bits Macitosh Plus compatible coector Iterface Amiga expasio bus compatible R Full auto-cofig compatibility 2.2 Power Requiremets 2.3 Evirometal + 5 Volts ±5%, 3 Amps. Max. Ambiet Temperature: 0 55 Deg. C. Relative Humidity: 20% 8O97o 2.4 Coector Pi Assigmets Table 2. through Table 2.3 list the pi assigmets for the cotroller board. For pi out ad defiitio for card edge coector refer to Amiga expasio architecture maual.

5 A2090A HARD DISK CONTROLLER Table 2. Coectors Jl ad 32 Disk Serial Data Pi Assigmets Groud Retur Sigal Pi Sigal Name Drive Selected Reserved Write Protected (Jl Oly) Reserved ' I Cartridge Chaged (Jl Oly) Groud (GND) MFM Write Data + MFM Write Data - Groud (GND) MFM Read Data + MFM Read Data- Groud (GND) Table 2.2 Coector JO Disk Cotrol Sigal Pi Assigmets Groud Retur Sigal Pi Sigal Name Head Select 3 Head Select 2 Write Gate Seek Complete Track Write Fault Head Select 2 Reserved Head Select r Idex Ready Step Drive Select Drive Select 2 Reserved Reserved Directio I Table 2.3 Coector CN, SCSI SCSI Coector (DB-25) Female Pi Name REQ MSG I/O RST ACK BSY GROUND Pi Name GROUND C/D GROUND ATN GROUND SEL DBP DBO GROUND DB3 DB5 DB6 DB DB DB2 DB4 GROUND N.C.

6 i! A2090A HARD DISK CONTROLLER 2.0 Referece [~j 8727 DMA Specificatio [ Commodore Amiga A5/A20 Techical Referece Maual Motorola 680 Techical Maual f-r Wester Digital WD33C93 SCSI Chip Maual America Natioal Stadard Committee X3T9.2 SCSI Specificatio 3.0 Fuctioal Descriptio The Amiga Hard Disk Cotroller basically cosists of three mai subsectios:. Host Iterface 2. ST506 Hard Disk Cotroller (HDC) 3. SCSI Cotroller 3. Host Iterface The host iterface is 680 compatible with direct memory access ad full auto-cofig capability. Data trasfers to ad from the host are usually made via DMA thereby allowig real time date trasfer rates of.6us/byte for the ST506 iterface ad up to 8s/byte for SCSI. Addressig for DMA operatios is provided by three exteral address couters. Before ay DMA operatio ca be performed each couter must be pre-set ad thereafter will be icremeted automatically. For iformatio o iitializig the DMA see sectio 4.0. The DMA is a Commodore custom LSI chip (8727) with byte to word fuelig ad a built i 64 byte FIFO. The iteral 64 byte FIFO permits real time data trasfer to ad from the host without holdig the bus for a etire sector trasfer. This provides very effective utilizatio of the bus. The average bus requiremet for the trasfer of a etire sector is 8.9us oce every 5.2us. This amouts to oly 7% over for CPU ad other bus masters. The iterface logic also provides full auto-cofig ad all I/O decode. For electrical specificatio ad detailed timigs refer to Commodore Amiga Techical Referece maual. 3.2 ST506 Hard Disk Cotroller (HDC) The ST506 Hard Disk cotroller is a itelliget backgroud cotroller capable of high level commad iterpretatio ad support of up two ST506 hard disk uits. This cotroller will be referred to i this documet as the HDC or the Hard Disk Cotroller. The processor for the HDC is a Z80A CPU, with up to 8K of PROM for firmware ad IK of RAM for variable data. Collec tively, the above compoets costitute the "itelligece" of the cotroller. The desig that has goe ito this aspect of the cotroller has bee to ehace performace ad icrease flexibility while reduc ig cost. As a result, the majority of operatios have bee placed i firmware. The oly fuctios performed by "hardware" are those that are too fast for the processor. i j The Z80A CPU ad its associated PROM ad RAM collectively perform the followig fuctios: ' <. Power up iitializatio 2. Diagostics 3. Error recovery 4. Error reportig 5. Error correctio 6. Commad processor 7. Disk select 8. Seek 9. Write precomp select, reduced write curret 0. Head select. Mappig 2. Logical to physical address traslatio Physical to logical address traslatio 3.2. The DJC Custom Chip The DJC is a custom LSI chip. It has bee desiged to hadle all serial data, state machie ad DMA fuctios as described below: ERROR CORRECTION CODE The error correctio polyomial is a 32-bit code capable of correctig up to -bit burst errors.

7 A2090A HARD DISK CONTROLLER I keepig with the overall desig philosophy, the ECC circuitry geerates the write sydrome ad validates the read without H requirig the processor to hadle the data. Calculatig this polyomial with the processor would seriously degrade the perfor- I i mace of the ST506 cotroller. Calculatig the reverse polyomial to correct bad data is doe by the processor. It is accomplished r*~ without ay measurable effect o performace because the operatio is oly doe after multiple retries ad as such is seldom ecessary. I I HEADER VERIFICATION Oce a disk has bee formatted, the DJC coverts the desired record address o the disk. The coversio is doe i terms I -( of head, track ad sector address, with a CRC code tested to further isure positioal itegrity. A compariso is the made j j of the header before a read or write fuctio is performed. TWO INDEX TIMEOUT p* This fuctio isures accurate cotrol over the umber of attempts to fid a header (i.e., it is ot "mislead" by coutig i false address marks). MFM ENCODE The DJC coverts all parallel data to serial ad the to MFM. This fuctio is followed by Precomp, if selected Selectable Precomp I Precomp, a "strig" of pulses is aalyzed to determie if they are arraged i the uique maer that could cause them to crowd oce writte o the disk. It also determies which way the crowdig would distort the pulses whe read. The write pulse stream is the shifted, early or late, to compesate for the crowdig coditios, which ormally occur o the iermost tracks of the drive. Uder the processor's cotrol, the DJC precomps the disk MFM data by usig exteral iductive delays. Precomp is selectable ad is desiged to shift the MFM data early or late by 2 aosecods to improve read margis. The use of this feature should be performed i cojuctio with the particular drive maufacturer's specificatio. H MFM Decode Data received from a disk drive is MFM, a self-clockig serial data stream which cotais a phase locked loop, lock detect, missig clock detect ad the data seperator. Whe the DJC asserts Read Gate, the 8465 data seperator will attempt to lock its phase locked loop o the read data. If this does ot occur withi 4.8 usec, the DJC will tur off Read Gate, causig the 8465 to be placed ito the low track rate for icreased stability. The MFM data is ow decoded ito NRZ data ad clock for the DJC. The 8465 decodes a missig clock bit ad a hexidecimal Al, FD or a Al, F8 i the syc field. This data idicates the start of a valid header or data field. Receivig ay other data causes the DJC to abort the read. Aother read would be tried after resycig the 8465 to 0 MHz Sector Format Figure 3.2 describes the format of a typical sector. Figure 3.2 Typical Sector Format I SYNC :A:FD:HEADER : WRITE SPLICE :SYNC 2:A:F8: DATA : 4 BYTE ECC I 4 BYTE HEADER ADDRESS MARK 52 BYTES BYTE = HEAD #; BYTE 2 = TRACK ADDRESS; BYTE 3 = SECTOR #; BYTE 4 = CRC Note:. Address Mark is a Hex with a missig clock pulse. 2. SYNC field is comprised of 6 bytes of zeros. 3. SYNC field 2 is comprised of 5 bytes of zeros.

8 A2090A HARD DISK CONTROLLER r Error Recovery Philosophy Extesive measures have bee take i the desig of the cotroller to isure reliable data. Selectable precompesatio circuitry ad a sophisticated data seperator with two trackig rates are a few examples. Additioal effort has bee made to reduce the probability of miscorrectio (of havig bad data flagged as corrected) through desig ad optios made available to the systems itegrator. I a write operatio the cotroller oly precomps the uique combiatios of data that might cause crowdig coditios o the disk. Shiftig data early or late by 2 sec is doe to retai as much of the 50 sec data widow as is possible. This reduces the probability of errors occurrig. I a read operatio the data seperator phase lock loop (PLL) provides two trackig rates, a high ad a low, which allows for quick sychroizatio with the header address i the first case ad stable data trasfer i the secod. The cotroller oly cotributes a maximum of 6 sec (typically 3 sec) of widow error out of the allowable error widow of 50 sec. This allows the disk drive to have up to 44 sec of jitter before error recovery/correctio is eeded. The cotroller uses a 32-bit error correctio code that eables a error correctio spa of up to bits. This computer-geerated code is cosidered superior to fire codes because it substatially reduces the chaces of miscorrectio while providig the full -bit correctio spa. I data recovery ad error correctio the ECC sydrome must be stable i order to perform a correctio. This isures that multiple attempts are made to recover margial data before correctio data is applied ad further reduces the probability of miscorrectio o log (greater tha 2-bit) error bursts. The sigificace of ot correctig data uless the ECC sydrome is stable is that ) oise iduced errors are ot corrected ad 2) real errors are corrected quickly without wastig time o useless retries. The user ca improve data reliability by mappig tracks with flaws ad by reducig the error correctio spa. The latter reduces the odds of miscorrectio o large errors (greater tha 2 bits) ad provides for early detectio of a degradig media. The cotroller ca be programmed to report or ot report "soft" errors, o reads that took multiple tries but did ot eed correctio. Moitorig soft errors is probably the best method of early detectio. A correctio spa of seve (7) bits is thereby suggested as a optimum i data itegrity. A alterate eleve () bit correctio spa could be used as a meas to retrieve the data before the track is mapped. 3.3 SCSI Cotroller The SCSI cotroller uses the Wester Digital WD33C93-SBIC which provides the actual iterface to the SCSI coector ad supports the full SCSI protocol miimizig host resposibilities. The WD33C93 is supported with a flexible architecture allow ig either the 680 (host) or the Z80A (board processor) to cotrol the WD33C93 operatios. Data trasfer ca be doe via DMA or host I/O. For detailed iformatio refer to Wester Digital WD33C93 maual. 4.0 I/O Defiitios The followig I/O addresses refer oly to offset locatio sice the actual board locatio i physical memory is cofigurable as described i the Commodore Amiga Techical Referece maual. Refer to this maual for details o auto-cofig I/O descrip tios. I/O locatios 0 hex through 42 hex are writte out as ybbles or 4 data bits (AD2-AD5). I/O addresses 50H - 68H are uique to this board ad will be described i this documet. Hex Locatio Defiitios /02 Boardtype ad size 04/06 Product umber 0/2 4/6 Mfg # high ad low byte 28/2A Optioal ROM vector high byte 2C/2E Optioal ROM vector low byte 40/42 WRITE READ 5 / 4 / 3 / 2 5 / 4 / 3 / 2 Iterrupt eable *SSEL MRESET *HCBP bit Iterrupt eable DON'T CARE MUST BE ZERO *CCBP bit ot defied INT2 PENDING ot defied ZERO ot defied ZERO ot defied INT FOLLOW Sigals uique to Amiga Hard Disk/SCSI Cotroller.

9 i A2090A HARD DISK CONTROLLER SSEL HCBP.CCBP 48H Used to select SCSI cotroller or to ST605 cotroller. High = SCSI, low = ST506. Host commad block poiter ad Cotroller commad block poiter; Used to had shake address of Commad block poiter to ST506. Base address register. 4. I/O addresses uique to board 50H 52H WRCBP/INTACK Multiplexed sigal. WRCBP strobes the commad block poiter register. INTACK clear INTP at ed of commad. PROCC Iterrupt ST506 cotroller to process commad. Write oly. Data value writte from host is XXXI hex to iitiate commad executio ad a data value of xxxo hex is writte from host to clear pedig iterrupt from 8727 (DMA). H 4.. SCSI Cotroller 60H 62H 64H 68H 4..2 Auto-Boot ROMS 80H-FFFFH CS Chip select for the WD33C93 SCSI chip. Used to write to the iteral address register ad read from the iteral status register. CS Chip select for the WD33C93 SCSI chip. Used to write ad read remaiig Cotrol registers i the WD33C93. SCSI PCSS Used to iitialize the 8727 (DMA) i SCSI mode. Refer to sectio 5.0 for 8727 commads. SCSI PCSD Used to pass data to ad from the 8727 i SCSI mode. Refer to sec tio 5.0 for trasfer procedures. To support AUTO-BOOT from hard disk the A2090A has two 28 sockets for autoboot ROMS. Two 8 bit wide ROMS are used to support the Amiga's 6 bit bus. ROMS ca be either 2764 or 2728 ad begi at the base address offset of 80H. r 5.0 Host Iterface Protocol 5. Iterface Protocol The host iterface is via a DMA cotroller. This DMA device is cotrolled by the Z80A o the disk cotroller board or 680 (host). O the host side there are couters for the address bus that are preset before the begiig of each trasfer. Three bytes must be writte for the 23 address lies (A23-A). The MSB (correspodig to A24) of the upper address latch is used to cotrol the host R/W- lie for DMA trasfers. This lie is set high to read from the host memory ad low if a write is iteded. The DMA logic, cotaied i oe chip, ca be cofigured to trasfer a sigle word (2 bytes) or 256 words (52 bytes). Trasfer are always o eve byte boudaries. The method of commuicatig to the DMA circuit is by two cotrol lies PCSS- ad PCSD-, cotrolled by the Z80 or 680. PCSS- is always strobed first to strobe i the "state" o the data bus. The state will determie the fuctio to be performed o the succeedig PCSD- strobes. Not all valid states eed to be followed by a PSCD- strobe ad for each state loaded, PCSDca be strobed ay umber of times. Whe readig the host status for istace, the expected umber of PCSD- strobes eed ot be give, but whe writig to the DMA cotroller the correct umber of PCSD- strobes must always be give. 5.2 DMA Commads The valid commads, for DMA operatios, are summarized i Table 5- o the followig page. All data values are listed i hex. Multiple states ca be strobed ito the DMA cotroller as log as o bus cotetio occurs. Notice that the state bits 4-0 are low i oe positio oly for all the valid states. This implies that ay state that does ot require trasfer of data by the followig PCSD- ca be combied ad set simultaeously. Hece a sigle word trasfer ad start DMA cycle ca be com bied as DE. Some states are mutually exclusive such as F7 (trasfer data to or from the FIFO) ad EF (readig the DMA status). Similarly state D6 is illegal sice word trasfer ad the FIFO path ope will result i BUS cotetio. State FC is permitted as log as the same data is to be writte i the DMA mid address latch ad DMA low address couter. Other such valid states ca be similarly derived.

10 A2090A HARD DISK CONTROLLER Tad/e 5-; DMA Data Strobed by PCSS- Brief Fuctioal DESCRIPTION Data Valid PCSD- (R/F) FB 0 Load upper DMA address latch F FD 0 FE 0 Load mid DMA address latch Load low DMA address latch; start DMA o risig edge F F of LDO; block mode XFER F7 Ope path to it. DMA FIFO (64 bytes) R EF 0 Read iteral DMA status R DB7 = if o DMA or DMA cycle complete DB6= if byte avail, from or to FIFO DB5 = if o FIFO overflow or uderflow 9F Force IREQ- to high impedace X BF 0 Commad complete sigal to host X DF 0 Set DMA ito a sigle word trasfer X 7F0 FF Reset DMA ad clear FIFO followed by FF to esure proper DMA reset. X X 5.2. Load Upper DMA Address Couter (FB) The LD2 output of the DMA chip is set low o the risig edge of PCSS- ad the set high o the fallig edge of PCSD-. This loads the R/W- ad the upper 7 address lies A23-A7 from the data bus ito a couter o the risig edge of LD2. This 8 bit couter eed ot be reloaded if its cotets are to remai ualtered i the succeedig operatios Load Mid DMA Address Couter (FD) Address lies A6-A9 are loaded ito aother couter i the same maer as above by the risig edge of LD. This 8 bit couter also eed ot be reloaded if its cotets are to remai ualtered i the succeedig operatios Load Low DMA Address Couter (FE) O the fallig edge of PCSD-, LDO is set high to load the address lies A8-A. The risig edge of LDO will start the DMA circuit. This also implies a block mode trasfer operatio, sice bits 7-4 are all high. O power-up the DMA cotroller defaults to the block trasfer mode. It should be oted that all three address couters metioed above are cascaded allowig for the cotiues trasfer of up to 64 Kbytes FIFO Access (F7) This state opes a path to a iteral FIFO that is 64 bytes i legth. The fallig edge of PCSD- will start to shift data out of the FIFO for a read or shift data ito the FIFO o the risig edge of PCSD- if the R/W- was set low with LD2. The DMA will iitiate host memory access, doe a word at a time, wheever the FIFO is half full. A typical memory access without ay wait states takes 4 cycles, each cycle beig about 40 S Read DMA Status (EF) The host DMA status must be read before iitiatig ay data trasfer, sice its FIFO ca be shared by aother device. At the ed of every word or block trasfer iitiated by the hard disk cotroller, the status must be read to esure successful data trasfer completio. Status is ot read after every word i a block trasfer. After the last byte, i a block trasfer, has bee strobed ito the DMA cotroller approximately 2 us are eeded to esure that the DMA status lies are all high. To read the status, ay umber of PCSD- strobes may be used before iitiatig aother DMA cycle. The DMA iteral status available after the fallig edge of PCSD- is iterpreted as follows: DATA BIT 7: This lie will be high if o DMA was requested or a DMA cycle was completed. After completio of a word or a block trasfer, this bit will be set high. A low idicates DMA busy status. DATA BIT 6: This bit is high if a byte of data is available to be read from the FIFO, or if there is a byte to be writte ad the FIFO is ot full. At the ed of a block write operatio to the disk, sice there are o more bytes available, this bit is set low.

11 I I A2090A HARD DISK CONTROLLER ' i DATA BIT 5: This lie is low if the FIFO overflowed or uder flowed. This may occur durig a disk trasfer if the DMA circuit does ot receive a bus ackowledge sigal from aother device o the 680 motherboard, before the FIFO becomes full or empty. Uder this coditio the FIFO is cleared by the Z80, before ay other data trasfer ca be iitiated. DATA BITS 4-0: These data lies will be logic zero Reset IREQ- (9F) '" ] This state will force IREQ- lie to high impedace. It is set low by the host Commad Complete Ackowledge (BF) This will cause the assertio of the host vectored iterrupt lie to its active low state to idicate the completio of a commad H by the HDC Word Trasfer (DF) r"j This will set the iteral DMA circuit ito a sigle word trasfer. O completio of the word trasfer, the DMA resets to ; [ a block trasfer mode. Hece this state must be strobed for every word trasfer desired Reset DMA (7F) i i This state, followed by state TF\ resets the DMA circuits ad clears the FIFO. This state should be strobed o power-up I ^ ad to clear ay FIFO uderflow or overflow coditios. r* 5.3 Host/HDC Commad Protocol i Commads are passed to the HDC through the DMA circuit. Whe the host requires a disk trasfer a commad block will be setup i the 680 memory followed by the host assertig the IREQ- lie low. The Z80 will the go through a sequece ^ for each IREQ as discussed below: 5.3. Step : Settig Up The DMA Address State FB is loaded ito the DMA circuit with PCSS- followed by PCSD- with the hex value of desired high ordered address. Bit 7 of the data bus determies the directio of the trasfer, a low will cause a write operatio to host ad a high will cause a read from host. The state FD is loaded ito the DMA circuit with PCSS followed by PCSD- with the value of desired address o the data bus. This sets up address lies A6-A9. State DE is loaded with PCSS- for a word trasfer. A value of 06 is loaded with PCSD- to poit to the 2th ad 3th bytes of the commad block. O the fallig edge of PCSD- the DMA word cycle will begi. Byte 2 must be FF before the commad is executed. I Step 2: Readig Data The state EF is loaded with PCSS- so that o the fallig edge of PCSD- iteral DMA status will be outputed. The data lies P) DATA7, DATA6, ad DATA5 are examied util they are high idicatig completio of the DMA cycle ad that data has shifted through the FIFO. For a block write operatio to the disk, DATA6 is examied util low. The HDC will sample the status for about 20 ms, util the data bus cotais EO or AO, before attemptig to clear the FIFO ad re-trasmit the block of data, if ecessary. If the FIFO caot be cleared after withi 20 ms, the commad will be termiated i the ormal maer, if possible Step 3: Readig The Commad Block If byte 2 is a FF, the rest of the commad block is retrieved by the HDC. This requires the executio of Step (LDO oly) followed by Step 2 four times. The data value for state DE of Step is icremeted from to 03, by the HDC for each word trasfer to get all eight commad bytes Step 4: Data Block Trasfer Block trasfers are iitiated as i Step except that the third state loaded is FE. The state DE was a sigle word trasfer. The directio of trasfer is determied by data lie DATA7 whe iitializig the high order address lies. Status is read by the HDC at the ed of every block or word trasfer, ad at the start of every ew commad.

12 A2090A HARD DISK CONTROLLER Step 5: Commad Completio To complete a commad status must be retured to the host. The status iformatio retured is that defied by the * Request Sese commad. To do this, 2 status words must be trasferred to the commad block. The host DMA is setup for a word trasfer, by settig the LD2, LD, ad the LDO couters similar to the read of the commad block byte 2 (see Step ). The four status bytes: ERROR, CODE, LUN:LADD2, LADD, ad LADDO are loaded ito the FIFO o the risig edge of PCSD-, a word at a time. As usual, the DMA status is examied, betwee word trasfers. If the commad, just executed by the HDC required a disk access, the the ADV (address valid) bit is set. Otherwise ADV =0 to idicate that the LSA, reported i the 4 byte status block, is meaigless. This completes the istructio. The host is ackowledged by writig state BF to set the host vectored iterrupt lie low. Also IREQ- is de-asserted by the HDC. 6.0 Commads 6. Commad Block "I I the 680 memory located at a address determied by Amiga DOS is a 6 byte commad block. The first byte received through the FIFO is the MSB eve byte, followed by the LSB odd byte. Durig the commad block trasfer phase, 8 bytes specifyig the commad are read by the HDC. The commad block is orgaized as follows: Table 6-: Host Commad Block BYTE 0 WORD 0 Commad Class OP Code 0 Logical Uit Number Logical Sector Address (High) 2 Logical Sector Address (Middle) 3 Logical Sector Address (Low) 4 2 Block (sector) Cout 5 2 Cotrol Byte (reserved i DMA spec) 6 3 High Order DMA DB Address (A23-A7) 7 3 Mid Order DMA DB Address (A5-A9) Low Order DMA DB Address (A-A8) Reserved 0 5 Reserved Reserved ADV Error Type Error Code 3 6 LUN LADD LADD LADDO ; [ H i! Byte 0 must be specified for all commads. Depedig o the value of Byte 0, each parameter i Bytes through 5 may require specificatio. Table 6.2 specifies the supported commads ad their parameters. It also icludes iformatio i data trasfers required durig executio. All other commads are reserved. 6.. Commad Class There are eight commad classes. Commad class 0 cotais the commads used i ormal operatio. Commad class 7 co tais the diagostic commads. Commad classes, 2, 4, 5, ad 6 are reserved for future use Operatio Code There are 32 operatio codes i each commad class. For a descriptio of all the available op codes see the Commad Descrip tio Sectio Logical Uit Number This is cotaied i the upper three bits of Byte specifyig oe of eight logical uit umbers. Logical uits 0 ad are hard disk drives 0 ad respectively. Logical uits 2 to 7 are reserved for future use. The HDC reports a ivalid commad if the logical uit umber is out of rage. However, for error reportig, all eve LUN's are treated as drive 0 ad all odd LUN's are treated as drive.

13 A2090A HARD DISK CONTROLLER 6..4 Logical Sector Address A logical sector address is a 2 bit usiged iteger that specifies a uique physical sector. The oe-to-oe correspodece betwee the set of logical sector addresses ad the set of physical sectors is computed by the HDC from the Cylider (C), Head (H), ad Sector (S) address, as well as the drive parameters, heads per drive (HD) ad Sectors per track (ST): L = ((( C * HD ) * H ) * ST) + S C, H ad S ca be derived from L, HD, ad ST as follows: r- S = L Modulo ST.: ( H = (L-S)/ST) Modulo HD C = (((L-S)/ST)-H)/HD T This field specifies a sector or the first sector for the Read ad Write Drive commads. Whe oly a track specificatio is I required, the sector umber implied by the Logical Sector Address is igored. Hece each format type commad begis opera tio at the begiig of the track cotaiig the specified sector. The HDC will report a ivalid commad, if the logical address specified is out of rage Block Cout The sector cout is a parameter for each data trasfer commad. It specifies the umber of logical sectors to be trasferred durig ay disk READ or WRITE operatios. The sector cout is a usiged, o-zero iteger. All zeros i the sector cout field specify a cout of 256. For a format commad, the umber of sectors to be formatted per track is specified by this byte. The iterleave factor eed ot be explicitly furished by the host, sice it is implicitly cotaied i the iterleave table furished by the host Cotrol Field The cotrol field is reserved for future use DMA Memory Address The ext three bytes, bytes 6, 7, ad 8, make up the 23 bit address which poits to the block of 52 byte to be trasfered via DMA. This block of memory cotais data bytes or specifies a address value as required by the commad to be executed. Sice the R/W- bit is part of the LD2 memory address couter, address bits A-A23 are shifted right bit by the HDC before beig stored for commad executio. H H 6..8 Status ad Error Bytes At the completio of each commad the HDC will retur status i the last four bytes (2-5) of the commad block. The status format is similar to that retured by the 'Request Sese' SCSI commad. This four byte block cotais error ad status iformatio pertaiig to the last block of data trasferred or a o-disk operatio executed by the HDC. The ADV bit will be set, to idicate a valid address, if the last operatio required a disk access, otherwise ADV = 0. The logical uit umber retured is simply the cotets of the logical uit field, where the error occurred, as defied i the drive cotrol block. For those commads that do ot take a logical uit umber as a iput parameter, the logical uit umber retured i the commad status byte is ot meaigful. A list of possible error codes, alog with their descriptios, follows: Error Bytes The logical sector address bytes are to be i the same format at that defied i the commad block. Bits 3-0 of the error byte is used for the error codes. Bits 4, 5 idicate the error type ad 7 is the ADV bit. Bit 6 is ot used presetly. Disk Drive Error Codes (Type 0) 0 No Error No Idex 2 Seek ot complete 3 Write fault 4 Drive ot ready 6 Track 0 ot foud 0

14 A2090A HARD DISK CONTROLLER i Cotroller Error Codes (Type ) H 0 Disk read I.D. error Ucorrectable data error 2 Address mark ot foud ^ 3 Sector ot Foud, Read 4 Sector ot Foud, Write 5 Seek error 8 Correctable ECC error *""] A Format error Commad Error Codes (Type 2) 20 Ivalid commad ^ 2 Ivalid sector address j 22 Soft header error i read 23 Soft header error i write 24 Soft data error I 28 Soft DMA error Hardware Error Codes (Type 3) 30 RAM failure (HDC) 3 ROM Checksum Error 32 Host DMA status error ^ Error Code Descriptio No Error A code of or 80 is retured if o errors were detected durig the executio of the last operatio. No Idex () The HDC does ot detect idex sigal from drive. Seek i Progress (2) This error code is oly retured by the test drive ready commad whe the target is a hard disk that supports buffered seeks. H It idicates that drive is busy doig a buffered seek. No other commad will be executed o the selected drive, util the seek i is completed. H Write Fault (3) This error code is retured by the hard disk drives. It idicates that there was write curret to the head whe the write gate was off. This is a very serious problem ad should be fixed immediately. No commad will be executed whe this coditio is detected. Drive Not Ready (4) No disk operatios are executed uless the drive is ready. Track 0 Not Foud (6) This error code is oly retured by the recalibrate commad. It idicates that the track 0 status from the drive did ot become active after the maximum ecessary steps towards cylider 0. Besides drive malfuctio, this type of error usually occurs if more tha disk drive is selected at the same time, either by the HDC or by the optio switches o the supported drives. Ucorrected Data Error () For a Wichester drive this error code idicates oe or more error bursts i the data field were beyod the error correctio code's ability to correct. It could also mea that the HDC was uable to obtai a match of two cosecutive sydromes withi eight read attempts. The sector data for the sector i error is set to the host, prior to ay retries ad correctio algorithms used. Address Mark Not Foud (2) It idicates that the header for the target sector was foud, but its address mark was ot detected. This is treated like a data field error, except that o data trasfer to the host takes place. If the error persists after 8 attempts, a auto-restore is performed, followed by a reseek, ad aother 8 attempts to read the desired LSA. Sector Not Foud, Read (3) The HDC foud the correct cylider ad head but ot the target sector. Sector Not Foud, Write (4) The HDC foud the correct cylider ad head but ot the target sector.

15 I A2090A HARD DISK CONTROLLER I.D. Not Foud (0) If the ID field caot be read correctly after all the retries have bee exhausted, this error code is set ad the operatio ter miated. The HDC searches for the ID field 8 times. Format Error (A) Durig a check track commad the HDC detects oe of the followig errors: ) Track ot foud. 2) Bad ID. Illegal Parameters (20, 2) These error codes, ivalid commad (20), illegal LSA (2), ad illegal LUN (22) are self explaatory. HDC RAM Error (30) Durig iteral diagostic the HDC detects a RAM error. HDC ROM Checksum Error (3) Durig iteral diagostic the HDC detects a ROM checksum error. Host DMA Error (32) This error code is set wheever ivalid status is read from the DMA durig ay data or commad access. For most operatios the status checked is E0 (hex), except for a block write. I this case the valid status checked for is A Commad Descriptio All commads executed by the HDC are summarized i the table below. Fields of the commad block ot specified are do't cares. Followig this summary is a geeralized descriptio of the commads. Table 6-2: Commad Summary Class LUN LADD It/ Cotrol Commad Descriptio Opcod Num (2) BCNT Optios Possible Error Codes Read Drive Status 0- RDS Restore to TKO , RDS Request Status Last Oper. Check Trk Fmt L R RDE, RDS, IDA i Format Track Read Drive L L B B S R,S IDA RDE, RDS, IDA Write Drive Seek Set Drive Param. 0A 0B OC L L B R,S 5, 9, RDS, IDA RDS, IDA 20, 32 Chage Commad Block Address OF 20, 32 Read Drive Log E5 0- L B R,S RDE, RDS, IDA Write Drive Log E6 0- L B R,S 5, 9, RDS, IDA Ik. Uit CC 20, 32 R = 0 Retries/ECC eable S = 0 Set correctio spa to 5 bits = Retries/ECC disabled = Set correctio spa to bits L = Logical Sector Address B = Block or sector cout required Read Drive Status (RDS) = 02, 03, 04, 20, 32 Illegal Disk Access (IDA) = 20, 2, 22, 32 Read Sector Error (RDE) =, 2, 3, 4, Read Drive Status (Class 0, Opcode 0) Actio Read the drive's status ad determie if drive is ready. For Hard disk drives supportig buffered seeks this commad is useful for determiig the first drive to reach its target track. The commad will be aborted, if the drive status read is icorrect. Possible Error Codes No error, ivalid commad, seek i progress, drive ot ready, write fault, DMA error. : 2

16 A2090A HARD DISK CONTROLLER Restore (Class 0, Opcode ) Actio The Restore commad positios the heads to cylider 0. It is usually issued by the host whe the drive has bee tured o, or before a format drive operatio is iitiated by the host. Possible Error Codes No error, ivalid commad, Track 0 ot foud, drive ot ready, write fault, DMA error Request Status (Class 0, Opcode 3) Actio Sed the host four bytes of error iformatio for the specified drive. The status of the last commad executed may have already set the error register but the executio of this commad will ot set ay ew bits. If however, the commad requestig the status is ivalid, the the previous commad status will be lost. Possible Error Codes No error, ivalid commad, last operatio status, DMA error Check Track Format (Class 0, Opcode 5) ii Actio Verify that the specified track is formatted with the correct umber of logical sectors. A multiple read commad is issued by the HDC to verify all the ID fields o that track ad the data read back from the disk is discarded. Retries may be eabled if desired. Possible Error Code No error, ivalid commad, ivalid sector address, IDNF error, drive ot ready, write fault, ivalid LUN, seek ot complete, DMA ot foud, ucorrectable data error, DMA error Format Track (Class 0, Opcode 6) Actio The format track commad is used for iitializig the ID ad data fields o a specified track. The curret cotets of the specified track are overwritte. This commad is useful for markig ay bad sectors or tracks after the etire disk surface has bee formatted. Assigmet of alterate tracks or simply ot specifyig bad logical addresses is best hadled by the host driver routies i the iterest of flexibility ad reducig oboard firmware requiremets. Possible Error Codes No error, ivalid commad, ivalid sector address, drive ot ready, seek ot complete, write fault, ivalid LUN, DMA error Iterleave Cosideratios Durig this commad the sector is set up by the host to cotai additioal parameter iformatio istead of data. Each sector requires a two byte sequece. The first byte desigates if a bad block (80) or good block () is to be recorded i the ID field. The secod byte idicates the logical sector umber to be recorded o the disk, as show below: Table 6-3: Iterleave Factor Table Data for a Iterleave factor of: (HEX) Addr i Hex H A OC D

17 A2090A HARD DISK CONTROLLER Addr i Hex Table 6-3: iterleave Factor Table (cotiued) Data for a Iterleave factor of: (HEX) OA OB OC OD OE OF OB 03 OC 80 OD OE OA OE OD 03 OF OA OB 7 OB OE OF OC A IB C ID OD OE OF 07 OA 20 0 OC IE IF 20 2 OF OB All XX XX XX XX Rest XX XX XX XX These umbers ca be from to 0 (hex), or 7 sectors per track or ay umber that the host wishes to specify that meets the drive track capacity. Bad block marks are show for sector umbers ad 4 i all four iterleave factors illustrated. The other requiremet of the host is to provide the logical sector umber. Usig this scheme, sectors ca be recorded i ay i terleave factor desired. Byte four of the commad block the specifies the umber of sectors to be formatted per track. Also the host is free to choose markig idividual sectors or etire tracks bad. At the ed of a track format, the host ca re-issue the commad, for formattig the track across head boudaries as show below: Table 6-4: Iterleavig Across Head Boudaries E OF 0 0 OF D OC 0E 0D OF 0E 0E OF 0 0 0B OC OD Usig the above spiral format approach, the HDC has approximately ms for ay processig overhead required. This ms loss i the : performace across head boudaries, assumig a disk rotatioal speed of 36 r.p.m. is reasoable. Across cylider boudaries, the : iterleave factor caot be maitaied because of the step rates ivolved. To format the etire disk usig the Format Track commad the host must update the buffer, if desired, ad re-issue the commad every track formatted. This is ot really a major advatage sice the host driver routies ca easily re-issue the commad i a loop util the etire disk is formatted. This gives the host total flexibility to format the drive usig ay clever algorithms for formats across head ad cylider boudaries istead of a caed approach. 4

18 A2090A HARD DISK CONTROLLER r i ii 6.2.5,2 Physical Track Format The data fields are filled with FF hex, ad the ECC is geerated as specified by the related codig optios. The Gap 3 value is determied by the drive motor speed variatio, data sector legth, ad the iterleave factor. The iterleave factor is oly importat whe : iterleave is used. The formula for determiig the miimum Gap 3 is: Gap3 = 2xMxS + K + E + V M = motor speed variatio (e.g..0 for ±970) E = 2 if ECC is eabled S = sector legth i bytes V = umber of overhead bytes required for the HDC betwee sectors K = 8 for a iterleave factor of =9 (for a iterleave factor of ) To maximize data read back efficiecy ad maitai the iterleave factor of oe, as closely as possible, it is required that the physical sector umbers be offset by a sector from track to track, (see table) so that the HDC has a sector legth available for overhead to switch heads while o the same cylider Read Drive (Class 0, Opcode 8) Actio Read the specified umber of cosecutive sectors begiig with the specified sector i the commad block to the host com puter. If ECC is eabled, ECC bytes are recomputed by the HDC. After the data is trasferred to the host, the recorded ECC bytes are compared to the geerated bytes to geerate the sydrome bytes. If the sydrome is o-zero, errors have occurred. Error correctio is ivoked by the HDC if two cosecutive sydromes match, otherwise a maximum of 8 retries are attempted by the HDC. Possible Error Codes No error, ivalid commad, ivalid sector address, ivalid LUN, IDNF error, bad block mark, address mark ot foud, ucorrectable data error, write fault, drive ot ready, seek i progress, DMA error Write Drive (Class 0, Opcode A) Actio The Write Sector commad is used to write the specified umber of sectors of data from the host computer to the disk, begi ig with the specified logical address i the commad block. The write operatio is idetical to the read, except for error hadlig ad readig the host status. Possible Error Codes No error, ivalid commad, ivalid sector address, ivalid LUN, drive ot ready, IDNF error, bad block mark, write fault, seek i progress, DMA error Seek (Class 0, Opcode B) Actio The Seek commad positios the R/W head to the cylider cotaied i the logical address. No ID field is read to verify start or ed positio. Seek It is primarily used to move the R/W head to the Shippig zoe for trasportatio of the hard disk. Possible Error Codes No error, ivalid commad ivalid sector address, ivalid LUN, drive ot ready, write fault, DMA error Set Drive Parameters (Class 0, Opcode C) Actio This commad poits to a 6 byte block of memory, specified by bytes 6 ad 7 of the commad block, that sets the followig parameters for both of the hard disk drives (logical uits 0 ad ): Table 6-5: Set Drive Parameters D7 D6 D5 D4 User Optios Num. of Heads D3 D2 Dl DO Step Rate CYL. Nums. MSN Number of Cyliders LSB Precompesatio Cylider / 6 Reduce Write Curret Cylider / 6 Number of Sector per Track 5

19 H H A20P0A HARD D/5X CONTROLLER If the above commad is ot executed after power up or every reset, the HDC will assume the followig default parameters: 306. = Number of cyliders (3 hex) 4 = Number of heads 28. = Startig write precompesatio cylider 28. = Reduce write curret cylider 3 ms = Step rate 5 = Maximum legth of a error burst to be corrected 7. = Number of sectors per track 8. = Retries & ECC eable The acceptable rage of values for these parameters are as follows: Number of cyliders 0-7 Number of heads Sector Numbers Startig write precompesatio cylider 5/. Maximum legth of error burst to be corrected 0/8 Retries If oe of the parameters is out of rage, the a "ivalid commad'' error code i geerated by the HDC. Bytes 2 thru 5 of table are self explaatory ad will ot be discussed ay further. User Optios This four bit field ca be used to specify optios as idicated below: Bit 7 = 0 5 bit correctio spa (default value) = bit correctio spa Bit 6 = 0 Retries & ECC eabled (default value) = Retries & ECC disabled Bit 5 = 0 Not Used Bit 4 = 0 Not Used Step Rate Step Rate 4 =. usec Step Rate 5 = 30 usec All Others = 3 msec Possible Error Codes No error, ivalid commad, DMA error Iitialize Uit (Opcode CC) Actio This commad with iitialize or set drive parameters of uit oly. This allows for the HDC to support two differet drive types at the same time. The actio of this commad is idetical to the actio of the 'Set Drive Parameter' commad oted above except that it will effect oly uit. For commad details see sectio Chage Commad Block (Class 0, Opcode F) Actio The Chage Commad Block is used to move the locatio of the commad block from the default o power up to a ew locatio. Bytes 6 ad 7 of the commad block are used as idirect address poiters for the begiig of a 7 byte block of memory orgaized as follows: Table 6-6: Chage Commad Block Address D7 D6 D5 D4 D3 D2 Dl DO i 0 A23 High Order DMA Byte 0 A6 A5 Mid Order DMA Byte A08 A07 Low Order DMA Byte 0 i 6

20 A2090A HARD DISK CONTROLLER Sice the host R/W bit, ad address bits A23-A7, form the data byte for the host LD2 - couter, the DMA high ad middle order address bytes are shifted right bit positio before beig used. Sice a copy of the previous address is ot maitaied, the commad status is retured to the ew address locatio specified ad ot the old oe. Possible Error Codes No error, ivalid commad, DMA error Read Log (Class 7, Opcode 5) Actio Similar to Read Sector except the ECC operatio producig the sydrome is ihibited i the HDC. Istead the HDC copies the recorded CHECK bytes from the disk ad passes them ualtered to the host. This commad is useful i debuggig ad verifyig the ECC hardware ad software. To do this first write ormally, ad the READLONG. The data or the check bits may ow be altered by the host ad writte to the disk usig the WRITELONG commad. If a READ commad were issued, the the HDC should ivoke error correctio o the data field ad correct it as log as the error iduced is withi the correctio capability of the ECC polyomial. Because there is o storage register o board, this commad is implemeted oly for diagostic purposes. Also ote that the 4 extra checkbytes are to be accessed directly by the host. Hece the diagostic tester used is required to support a 56 byte block trasfer istead of the stadard 52 byte block trasfer supported by the Amiga system. p Possible Error Codes No error, ivalid commad, ivalid sector address, ivalid LUN, IDNF error, bad block mark, address mark ot foud, write fault, drive ot ready, seek ot complete, DMA error. rm Write Log (Class 7, Opcode 6) j Actio The Write Log commad fuctios similarly to the Write Sector commad except the ECC operatio of computig the ECC word is ihibited i the HDC. Istead, the HDC accepts a 32 bit appedage from the host ad passes it ualtered to the DJC I I to be writte o the disk after the data. This commad is useful for diagostic purposes oly. It allows the geeratio of ; ' a sector cotaiig a correctable ECC error. See the Read Log commad descriptio for operatio details ad system requiremets. Possible Error Codes No error, ivalid commads, ivalid sector address, ivalid LUN, IDNF error, bad block mark, fault, seek ot complete, drive ot ready, DMA error. A2090A HARD DISK CONTROLLER ADDENDUM Your ew A2090A Hard Disk Cotroller card icludes two autoboot EPROMs. These EPROMs are ONLY to be used whe the Kickstart Versio.3, or later, ROM is preset i your Amiga 20. Use of these ROMs with Kickstart Versio.2 may iterfere with the operatio of your computer. Istallatio of the EPROMs should be performed by a authorized Commodore Service ceter. Commodore shall ot be respo sible or liable for ay damages whatsoever caused or occasioed by improper istallatio or use of these EPROMs. Istallatio of the Autoboot EPROMs The two Autoboot EPROMs for the A2090A are istalled i chip locatios U50 ad U5 (directly uder the Jl ad J2 cable coectors). The HI, or Eve, EPROM must be istalled i U50, while the LO, or Odd, EPROM goes i U5. There is letterig o both the EPROM ad the Cotroller board so that you ca differetiate which locatio is HI (Eve) ad which oe is LO (Odd). To isert the EPROM: ) Make sure the EPROM is facig the correct directio. The EPROM is rectagular ad will be iserted to coform to the outlie draw o the board. However, there is a small otch o o edge of the EPROM (oe of the shorter edges). This otch must alig with the otch i the board's socket. 2) Oce you have the EPROM orieted i the proper directio, alig the pis of the chip with the holes i the socket. 3) Carefully ad very slowly, begi to press the EPROM ito place. Costatly check to make sure that all the pis are goig ito the holes ad that oe of the pis are out of aligmet. The EPROM is fully iserted whe it is just about flush with the socket. 7

21 A2090A HARD DISK CONTROLLER Autobootig with the A2090A NOTE: YOU CANNOT AUTOBOOT WITH THE A2090A UNTIL THE KICKSTART VERSION.3, or later, ROM HAS BEEN INSTALLED IN YOUR A20. Whe your A20 has the Kickstart Versio.3, or later, ROM istalled, you ca autoboot directly from your hard disk. This meas that you will ot have to isert a Workbech, or other bootable, disk ito our computer whe you tur it o. As log as your hard drive has bee property prepped ad formatted, as explaied i the accompayig user's guide, you will be able to autoboot by simply turig o the power to your A20. Isertig a floppy disk ito the iteral floppy drive (dfo:), will override the autobootig from the hard drive. This allows you to boot from a floppy disk wheever you desire. Correctio to page of the A2090 Hard Disk/SCSI Cotroller User's Guide: Please add the followig hard drives to the list of models available for use with the Amiga 20: ST506 Drives SCSI Drives Miiscribe 8425F Coor CP340 Miiscribe 805IS Quatum ProDrive 40S Rodime RO3057S Type B Seagate ST25N* * You caot autoboot with a Seagate SCSI hard drive ad a A2090A Cotroller Card because of the log iitializatio process i the Seagate power-up sequece. (This pertais to all Seagate SCSI hard drives, icludig the drives listed o page of the Hard Disk/SCSI Cotroller User's Guide.) Correctio to page 34: The iformatio below replaces the iformatio i the "Usig Multiple Hard Disk Cotrollers" sectio (page 34) of the A2090 Hard Disk/SCSi Cotroller User's Guide: [j Multiple Cotroller Boards ' It is possible to istall more tha oe A2090/A2090A Hard Disk Cotroller ito the Amiga 20 if you would wat to use more tha two ST506 hard disks ad/or seve SCSI devices with your Amiga system. For each additioal Cotroller, you ca istall up to two ST506 hard disks ad/or seve SCSI devices. The driver ame assigmets for hard disks coected to additioal Cotrollers follow a two-pass cofiguratio procedure, explaied below. Bidig Driver Names to Cotroller Boards The first pass of the driver cofiguratio procedure occurs for the A2090A Autoboot boards. (These boards MUST HAVE valid Autoboot EPROMs istalled.) The secod pass occurs for A2090 boards ad A2090A boards without the Autoboot EPROMs istalled; this pass takes place whe the BidDrivers program of your startup-sequece is executed. Durig the first pass of the driver cofiguratio process, Autoboot A2090A boards are cofigured sequetially, begiig with A2090A board i the slot closest to the processor (earest to the power supply) ad cotiuig outward for each Autoboot board i tur. The first board is assiged to the "hddisk.device," the secod assiged to the "iddisk.device," ad additioal boards are assiged to the "jddisk.device,""kddisk.device," ad so o. The secod pass occurs durig the executio of BidDrivers. A2090 (o-autoboot) boards are also cofigured sequetially startig with the A2090 board closest to the processor ad cotiuig outward. All o-autoboot boards receive a assig met to a sigle driver ame. This ame correspods to the ext ame available after the first pass. For example, if you had two Autobootig A2090A boards ad two A2090 boards istalled, the assigmets would be as follows: A2090A board closest to processor hddisk.device 2d A2090A board iddisk.device Both A2090 o-autobootig boards jddisk.device These assigmets must be icluded i the MoutList etry for each ST506 or SCSI device. For istace, "device = hddisk.device" or "device = jkkisk.device". Assigmet of Amiga DOS Names to Hard Disks or SCSI Devices To create uique AmigaDOS ame assigmets to the actual hard disk devices, a similar two-pass procedure is followed. First, all hard disk drives coected to A2090A boards are amed, begiig with the A2090A Cotroller closest to the processor ad cotiuig outward (as described above). The, the devices coected to the A2090, o-autobootig, boards are amed; agai, startig with the board closest to the processor ad cotiuig outward. 8