Embedded Flash for Automotive Market. Increasing demand for performances, endurance and reliability in harsh conditions. Challenges and solutions

Transcription

1 Embedded Flash for Automotive Market. Increasing demand for performances, endurance and reliability in harsh conditions. Challenges and solutions Fausto Piazza Silicon Technology Development envm Memories Workshop on Innovative Memory Technologies May 28, , June 29, MINATEC, Grenoble, France

2 envm in automotive: Outline Market requirements Available NVM options Challenges for 1T Flash Techno Results Conclusions 1

3 envm in automotive: Example of Product Main CPUs - Three identical dual issue, 32-bit CPU core complexes 4.4MB on-chip flash 128KB on-chip general-purpose SRAM Multi channel direct memory access controllers (edma) 5 x Interrupt controller (INTC) (one per CPU) Dual Phase-locked loops Dual Crossbar switch architecture On-chip voltage regulator controller regulates supply voltage down to 1.2 V for core logic Self Test capability 2

4 Marketing requirements Low costs usage of consolidated technologies with limited number of devices (and therefore limited number of masks) Optimized IPs architecture to cover all differentiators cut modularity, blocks re-use Safety requirements no content corruption auto-test system (digital, analog, address decoding) Security end-user is not supposed to modify protected zone Reliability 0-ppm target, no matter the market segment, full Temp range ECC, robust designs, severe screening at testing each single customer return to be analyzed 3

5 envm in automotive: Marketing requirements CODE DATA Size, (kb) MB 1-8 (2 x 16) - (4 x 64) Sector, kb Access Time (ns) (5 20) ~ 100 Erase Time (ms) 128 (16) kb sector < 1000 ( < 200) Write Time (us), 128(32)bit ~50 (~50) Icc-read/modif (ma) 30/30 10/10 Cycling 1k 100k 1M 4

6 Marketing requirements: Reliability Endurance: up to 500 kcyles at product level Data Retention: 10 85C, <1ppm failure rate at product level Increasing data memory size Severe Temperature User Profile Time (hours) Temperature (C) 5

7 envm in automotive: Outline Market requirements Available NVM options Challenges for 1T Flash Techno Results Conclusions 6

8 envm: technology benchmark vs automotive Flash Split-FG Split- Monos Split - TFS PCM ReRAM MRAM Cell type 1T-Nor 1.5T 1.5T 1.5T 1T-1R 1T-1R 1T-1R Cell size,f ? granularity NVM techno impact Sector (Page) Page Page Page 1bit 1bit 1bit HV+NVM HV+NVM HV+NVM HV+NVM NVM NVM NVM Endur Wr < ? ? 10 17? cycled Automotive Maturity good good fair fair low? fair code & data Code (data?) Code? N.A. N.A. N.A. N.A. PROs Reliab, envm std Tacc, envm std Tacc Tacc Tacc, granul.,cost Endurance, cost Endurance CONs Design complexity cycling cycl New techno New techno High consumption Stack integration 7

9 TFS vs. 2T Approach Macrocell Area (arb. Units) 90nm node TFS low current programming technique and no need of negative Voltage is taken into account for the charge pump sizing. Analysis has been focused on code storage. For data storage, 1T Flash needs to add a 64K data flash block for small sectors. 8

10 envm in automotive: Outline Market requirements Available NVM options Challenges for 1T Flash Techno Results Perspectives 9

11 Cost of Manufacturing Number of Extra Masks for Flash (and HVMOS): from 6 to 10 depending on the technological skills and on the required Flash and MOS performances. Optimisation of Flash Cell Layout: area vs. performances On embedded products presently in production (about 512 kbyte) the NVM macrocell is occupying 30%-50% of the floor plan. Array efficiency for present embedded cuts is about 40% for a macrocell optimized in area and about 20% for a macrocell optimzed in performances. Those figures are rapidly improving with larger memory cuts. Multilevel is possible but not convenient for typical embedded cuts (close to upper limit). Degradation of access time. 10

12 Electrical Specifications Single Cell Reading Power 10 ua 10 ma Time Voltages Vd~1V; Vg~5V Macro Cell about 50 ns possibility to go down to 20 ns with pipeline techniques 10ns Single Cell Programming (HCI) Macro Cell Power 100 ua (Automotive) 20mA (Automotive) (parallelism by 64) Time 5 us 20 us / 64bit (Automotive) Voltages Vd~5V; Vg~10V Single Cell Erasing (FN) Power Negligible Not relevant Macro Cell Time 100 ms (Automotive) 5 s / MByte (Automotive) (80% soft prog.) Voltages Vg ~ -10V; Vb~10V 11

13 CMOSM55: Main Features Embedded Flash Process Family DERIVED from 55nm BASELINE TECHNOLOGY CMOS055 CMOS055 option available: Low Power Available supply voltages: 1.2V, 3.3V, 5V Flash cell (poly floating gate cell): 0.135µm² GO1 MOS aligned to C55 offer GO2 MOS for 3.3V (65A GateOx) HV MOS for 5V IOs and ~9 V prog/erase management (150A GateOX) (based on M10 offer but with L scaling 0.72µm -> 0.65µm) Flexible number of metal level (5M:3X0Y1Z & 6M:4X0Y1Z) AlCap Routing 12

14 Modular Process ST Modular Flow: interaction between Flash + HV MOS and LV MOS is minimized (Ni silicide, spacer cell sealing, ). Flash + HV MOS (less aggressive scaling, higher thermal budget) first LV MOS flow almost unchanged with respect to the bulk flow. Same flow architecture as compared to previous technology nodes. 13

15 ST 55nm e-flash cell (0.135µm 2 ) Cell area µm2 (X=0.31 Y=0.43) Active width 0.14 µm Gate length 0.18 µm Gate spacing 0.26 µm Metal 1 space 0.14 µm Metal 1 space 0.31 µm (0.16 dist. 0.15) Attribute via1 metal Tj Data Retention -40C to 175C Product lifetime 0.43 metal2 poly Endurance >100K cycles Random Read Time <15ns poly1 Erase Time <1sec active area Erase/Prog Method FN / hot-e Write Time <10us Program Power per Bit uA/bit

16 LV MOS alignment to reference process -6.5 Nlvt Idsat-Ioff 1000x60 Q108KM C -7.5 Nsvt Idsat-Ioff 1000x60 Q108KM C -9.5 Nhvt Idsat-Ioff 1000x60 Q108KM C Ioff (log A/um) Ioff (log A/um) Ioff (log A/um) Idsat (ua/um) Idsat (ua/um) Idsat (ua/um) -7 Plvt Idsat-Ioff 1000x Psvt Idsat-Ioff 1000x Phvt Idsat-Ioff 1000x60 Ioff (log A/um) Q103IRM M Idsat (ua/um) Ioff (log A/um) Q103IRM M Idsat (ua/um) Ioff (log A/um) Q103IRM M Idsat (ua/um) 15

17 Flash cell performance 100 FCVTW1_136I 100 FCVTE_136I 100 FCGAIN_136I 90 Q109MAK 90 Q109MAK 90 Q109MAK Cumulative % Cumulative % Cumulative % VT Pgm (V) VT Erase (V) Cell Gain VD=0.5, VG1+0.5 (µa/v) Program Vth, Erase Vth, and gain are in target at parametric testing Gain variability to be improved

18 CMOSM55 test chips strategy PAD FRAME ROW LOGIC RYDE FAILURE MECHANISMS BLOCK SA COL LOGIC PAD FRAME PROMOM55 SRAM 6Mb Comp iler Misc cuts «core logic mode» StdCells (ALLCELL + GENOM RingOsc.) eflash 12Mb KRYPTON µ-ctrl «flash mode» IO ring, WB final pitch 60µm ANNA 128Mb NAMASTEM55 (SPREG, SPHD) RYDE PROMO ANNA NAMASTE Process development Process qualification (eflash cycling) Dsgn Pltf validation (memories) Dsgn Pltf qualification FE/BE compatibility - 17

19 Endurance on Macrocell 0.7V 1V 18

20 Endurance on Macrocell (from 90nm node) 19

21 Summary Automotive is an expanding market in particular for embedded nonvolatile memories. Several critical requirements have to be fulfilled to serve the market in term of time to market, cost, IP variety and reusability, security, safety, and reliability. In particular, reliability, have to be granted in increasingly demanding conditions in term of temperature, duration and area. Because of the fact that next generation nonvolatile memories are not yet mature for this kind of market, we believe that 1T flash is a (the) suitable choice for next generation(s) of automotive products. Some data have been shown on 55nm eflash technology to support this statement. 20

22 envm for automotive Thank You! 21