Flash TOSHIBA TOSHIBA

Transcription

1 Flash

2 VOLATILE Mobile Application Low Power SDRAM Pseudo SRAM High Speed Application embedded edram PLEDM FBC memory Low Power Low Power SRAM QDR SRAM DDR SRAM Sigma RAM FeRAM High Speed MRAM OUM Universal FCRAM RLDRAM DDR-SDRAM Rambus DRAM Large Capacity NOR Flash MLC NOR NON VOLATILE NROM Storage NAND Flash MLC NAND 3D ROM Non Volatile RAM Endurance DRAM SRAM >10 15 >10 15 NOR NAND FeRAM MRAM (>10 15 ) OUM >10 12 WRITE 15n-50n 1n-100n 10us/B 10MB/s 40n-100n 20n-100n 10n-50n Read 15n-50n 1n-100n 20n-100n >10MB/s 40n-100n (20n-100n) 20n Cell Size Density (bit) 8F 2 512M/1G F 2 36M/72M 6-12F 2 (MLC) 256M/512M 4-6F 2 (MLC) 4G/8G 10-20F 2 64M/128M Power supply (1.8Vvoltage 1.8V-2.5V 1.2V-1.8V 1.8V-2.7V 1.8V-2.7V 1.8V-2.5V 3.3V) Program voltage 1.8V-2.5V 10V 18V 1.8V-2.5V Power Write/Read 1 / 1 1 / 1 >10 / 1 >10 / 1 1 / 1 >10 / 1 Interface DRAM SRAM SRAM Like NAND SRAM Like SRAM Like (8-15F 2 ) (64M/ 256M) (5-8F 2) (64M) (1.8V- 3.3V) (>10 / 1) (SRAM Like)

3 WL BL Plate (static) WL BL Plate (plus) WL BL WL BL DRAM DRAM FeRAM FeRAM MRAM MRAM OUM OUM Capacitor Capacitor Capacitor Capacitor (Ferro electric) (Ferro electric) Magnetic Magnetic Tunnel Tunnel Junction Junction Chalcogenide Chalcogenide Glass Glass 1 Data Data 0 Data Data WL Source Drain NAND NAND Floating Floating Gate Gate Merit Merit Demerit Demerit,, Logic, Logic Logic NOR NOR D Memory D Memory NROM NROM FBC FBC Floating Floating Gate Gate Anti Anti-Fuse Fuse ONO ONO Body Body 1 Data Data 0 Data Data WL Source Drain NAND NAND Floating Floating Gate Gate WL Source Drain WL Source Floating WL Source Drain WL BL P+ N+ P+ N+ Merit Merit Demerit Demerit OTP Logic Logic SOI SOI

4 NAND : : NOR - - DVD -Set TOP Box BIOS -PC : :

5 Principle of Flash (1) Id-Vg (2) Vt distribution (3) Cell Condition CONTROL GATE VOLTAGE(Vcg) 5V 1V 0 Program SHIFT Erase Drain Current (Id) Vth(V) Program Erase Number of bits Floating Gate Source (Vs) Source (Vs) Drain (Vd) (b) Program (a)erase Control Gate Drain (Vd) Program / Erase Method Electron Injection V pp V pp Program Current < 1uA V D Program Current < 2-5mA -Page program S D - Byte program FN tunneling Hot Electron Electron Emission V PE High V PE ( 20v ) V PE LowV PE ( 12v ) HighV PE ( 20v ) V PE FN tunneling - High Speed Erase ( 3ms/Block ) S Edge-FN tunneling D - Low Speed Erase (1s /Block) S Poly-FN tunneling D - High Speed Erase (3ms/Block)

6 Vth Cell Function NOR SANDISK AND NAND PROG. Hot Electron Hot Electron Edge-FN tunneling FN tunneling ERASE Prog. Speed Access Mode Edge-FN tunneling Poly-FN tunneling FN tunneling FN tunneling 0.1MB/sec 0.5MB/sec 2.0MB/sec Very Fast 2.5MB/sec Random Serial Serial Serial Cell Array NOR SanDisk AND NAND Bit line(metal) Bit line /Source line(metal) Word line(poly) Contact Erase gate(poly) Word line(poly) Word line(poly) Word line(poly) Source line (Diff. Layer) Sub Bit line (Diff. Layer) Unit Cell Unit Cell Unit Cell Unit Cell Source line (Diff. Layer) Source line (Diff. Layer) Simplest wiring Smallest area

7 Physical Bit Cell Structure F: Design Rule NOR SanDisk AND NAND Layout Crosssection Bit Cell Size 10F 2 9F 2 8F 2 4F 2 Simplest Smallest Is 4F 2 the Final Cell Size? 4F 2F 3F 2F 2F 2F? AND String 2 Diffused Lines 2F 4F = 8F 2 Common Source 1.5 Diffused Lines 2F 3F = 6F 2 NAND String 1 Diffused Line 2F 2F = 4F 2 New String 0.5 Diffused Line

8 Cell Size Trend 10 LOCOS SA-STI MLC Cell Size 1( um2 ) SA-STI ONO Tunnel Oxide LOCOS Multi Level Cell 0.1 ONO Tunnel STI Oxide Start of Mass Production

9 Top View NAND Flash memory cells View Equivalent Circuit Low Ion / Ioff Ratio is Allowable Selected Block Non-selected Block 3.5v 3.5v v 3.5v v v v v Bit Line Selected cell (A) Select Transistor shut down from BL Ion Ioff cell cell Vcg of Selected WL OK Short Channel Effect is negligible! Scaling of Gate Length is easy

10 STI NAND Cell Structure Mask SiN 0.25µm 0.30µm SiN Spacer SiN 1st poly-si 0.15µm 0.4µm Tunnel Oxide P-well (a) 2nd Si poly- (c) Mask SiN Control Gate Inter-poly (ONO) STI (b) (d)

11 Cell Micro-Photograph

12 NAND Flash Memory Capacity 1996 MLC Technology MLC : Multi Level Cell 128Mb SLC 0.4um MLC NAND SLC NAND Design Rule 256Mb Mb SLC 0.25um Maximum 1Gbit MLC 512Mb SLC 0.16um 2Gbit MLC 1Gb SLC 0.13um 4Gbit MLC 2Gb SLC 0.10um Large Capacity Year (0) Number of Bit (1) 2NAND(1 bit/cell) (1,0) (0,0) (1,0) (1,1) NAND(2 bit/cell) ECC

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14 CLAMP SEN1 M1 N1 BLT1 PRE SEN0 BLS1 BL1 BL0 BLT0 SGS BLS0 VSH

15 NAND vs. NOR : Fast Program 2.3 MB/s 6.8 MB/s

16 Fast Program with Write Cache Total Program Time Data Load Time + Actual Program Time 528B PageTprog. = 26.4µs + 200µs 2KB PageTprog. = 26.4µs µs Row Decoder Page Prog. Data Load 1KB 1KB Write Cache and Page Size Program Speed (MB/sec) Appropriate Density 64M 256M With Write Cache MB/s 6.91 MB/s 1G Page Size Without Write Cache 4G 16G

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20 Digital Consumer Industrial Use Smart Media TM SD Card Multi Media Card Compact Flash TM ATA Card NAND Flash Drive ~128MB ~128MB ~64MB Thin! Small Small Lowest Cost Secured Thin ~1GB Mid Capacity Compact ~2GB ~2GB Large Capacity Large Capacity PC Card Compatible w/ HDD NAND No controller inside NAND + Controller Digital Camera Mobile Phone PDA Note PC Car NAVI FA Robot ATM / CD MP3, IC Recorder Digital CAM Coder Networking Server POS System

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22 512MB 128MB Flash Disk Target Price THNIDxxxxBA (2.5 ) THNIDxxxxBB (3.5 )

23 128MB 64MB 32MB 16MB 8MB 4MB CD 1/1 MP3 / AAC / Twin VQ / Atrack3 Toshiba Axia Maxell Hagiwara syscom / CD Ripping Kiosk Diamond Multimedia Sony / SD / ID SmartMedia Creative

24 PS2 $14,000 $12,000 $10,000 $8,000 $6,000 $4,000 $2,000 $ NOR Combo NAND Source: web-feet Research

25 (1,0) (0,0) (1,0) Number of Bit (1,1) Unit Cell 4F 2 FN-Tunnel Small Current (0) (1) Number of Bit Byte EEPROM NOR NAND? Dismiss Byte Reprogram Dismiss Random Read Attain Small Cell Size Attain Small Cell Size Attain Fast Program

26 Semiconductor Company