FPGAs & Multi-FPGA Systems. FPGA Abstract Model. Logic cells imbedded in a general routing structure. Logic cells usually contain:
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1 s & Multi- Systems Fit logic into a prefabricated system Fixed inter-chip routing Fixed on-chip logic & routing XBA Partitioning Global outing Technology Map. XBA XBA Placement outing 23 Abstract Model Logic cells imbedded in a general routing structure Logic cells usually contain: AM AM AM AM AM AM AM AM AM AM AM AM 6-input Boolean function calculator Flip-flop (-bit memory) All features electronically (re)programmable
2 eal Architecture Altera Stratix V Note: Most pictures following courtesy of Mike Hutton/Altera Inc. 25 Altera Stratix V Device Floorplan Logic Blocks Multipliers & DSP Embedded Memories Clocking Logic I/O Protocols
3 27 The k-input LUT (e.g. k=4) D C B A Y LUT-mask a b c d + abcd + abc d = = x89 28 Adaptive Logic Module
4 Stratix V ALM Stratix V ALM Modes
5 LAB Interface H,V LAB lines local lines global signals H24 V6 Secondary Signal Generation V4 H4 H4 LEA LEB LE LEC LED H24 V6 V4 H4 H4 LEA LEB LE LEC LAB LED Input Output 2 Hierarchy: LAB / Cluster H channel LAB V channel LE LAB lines 22
6 Global outing outing (Detailed) Xilinx 4 Series
7 Altera Stratix V Device Floorplan Logic Blocks Multipliers & DSP Embedded Memories Clocking Logic I/O Protocols Memory in Stratix Devices MLABs M2K Blocks External Memory Change LABs into dual port memories x32addr by 2bit x64addr by bit FIFO Buffers Shift egisters Delay Lines Small OMs 2Kbit on-chip blocks dual port w/parity 6Kaddr by bit 8Kaddr by 2bit 52addr by 32bit Large on-chip storage Intermediate results Caching & data reuse DAM, SAM, & FLASH interfaces Multiple Gbytes Huge Datasets Longer-term storage More Bits for Larger Memory Buffering More Data Ports for Greater Memory Bandwidth
8 DSP Blocks (8-bit mode) DSP Blocks (High-precision mode)
9 Putting it all Together Stratix V Statistics (5SGSD5H2F35I3LN) Logic ALMs (4xeg, 4x4LUT, ): 72K DFFs: 69K 4-LUTs: 69K Hard Multipliers: 3,8 (8x8),,59 (27x27) Memory 64xb MLABs (uses ALMs): 4.3K (344KBytes) M2K blocks: 2,4 (4.9MBytes) I/O, Clocks PCIe hard IP blocks: DD3 Interfaces: 4 4.Gbps transceivers: 24 Clock Generators (PLLs): 24
10 oles Digital logic implementation & prototyping Multi-mode systems Change functionality for different applications Logic emulation Stream-based computing aw Image Data Processor acceleration Processed Image CPU 22 Partitioning For Multi- System: Break logic into individual s espect inter- communications Similar to placement Techniques Multi-level partitioning (xbars) Simulated Annealing XBA XBA XBA 222
11 Virtual Wires Multi- systems typically pin-limited, not logic limited : up to Million logic gates, 52 I/Os. Partitioned circuit components might be: x( Million gates, 5, I/Os) x(, gates, 5 I/Os) Solution: 2x(/2 Million gates, 2,5 I/Os + time division multiplexing on I/Os) Pad Pad egister Control FSM Control FSM 223 Global (Inter-) outing oute from source to destination using fixed resources Similar to Aphyds Global outing, but with fixed capacities Maze, Steiner, etc. all can be applied Must deal with potentially non-geometric distances XBA XBA XBA 224
12 Technology Mapping Take circuit and map it into the basic elements of the 5-LUTs Must consider multiple factors logic decomposition logic replication reconvergent fanout A B C D E F G H I J K L M N X Y Z A B C D E F G H I J K L M N X Y Z 225 Placement Assign logic blocks to specific chip locations Virtually identical to Aphyds Placement Seek to minimize routing distance, congestion 226
13 outing Must pick the individual resources to use to carry a signal fixed capacity potentially non-geometric distances balance demands of multiple routes Pathfinder (McMurchie, Ebeling) Convert routing architecture to graph Ignore congestion change penalties and iterate Use maze + A* routing Integrate performance and congestion avoidance into one algorithm 227 Pathfinder epresent all interconnection resources as a directed graph Pin permutations on LUT inputs also captured 3-LUT DFF outing sketch: Each iteration rip-up and reroute all signals independently. esources currently used by another net cost more Between iterations increase cost of resources that are shared -> Over time, signals bid on preferred route, negotiating a compromise 228
14 s & Multi- Systems Fit logic into a prefabricated system Fixed inter-chip routing Fixed on-chip logic & routing XBA Partitioning XBA XBA Global outing Technology Map. Placement outing 229 CAD & Physical Design CAD = Computer Aided Design Complexity of today s circuits requires computer support for most design tasks CAD split into Synthesis, Physical Design Synthesis = translating designer requirements into a circuit graph PD = translating circuit graph into layout ( blueprint ) for fabrication Partitioning Floorplanning Placement Global outing Detailed outing Compaction 23
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