Reconfigurable Architectures for Real World Applications

Transcription

1 Reconfigurable Architectures for Real World Applications José Andrés Otero Marnotes Universidad Politécnica de Madrid

2 Reconfigurable Devices TWO CHOICES Custom Solutions Commercial FPGAs Specific Solutions Different Granularities Academic Environment Processing Capabilities Flexibility Closer to Industry GPP Trade-off between Flexibility and Performance Flexibility Reconfigurable systems ASIC performance 2

3 Researchers involved in the Reconfigurable Systems Area at CEI Professors Teresa Riesgo Eduardo de la Torre Félix Moreno Jorge Portilla PhD candidates Rubén Salvador Wei He Gui Xuan Liang José Andrés Otero Master level Eduardo Lezcano Juan Valverde PFC level Carlos Pizarro Javier Mora Miguel A. Lombardo Iván Flores Alberto Vidal 3

4 Current Projects: dr.simon Multimedia Applications Scalability by means of reconfigurability Dynamic and Partial Reconfiguration Multimedia Networks Scalable Video Coding Intelligence on Chip 4

5 dr.simon.hardware for Scalable Video Adaptation to different Devices SVC DECODER Adaptation to the communications network Variable Speed Decoder Adaptation to the device power consumption At run-time 5

6 Scalable Deblocking Filter for SVC Input FIFO Input FIFO Input FIFO FU11 FU42 FU13 FU21 FU32 FU23 FU31 FU22 FU33 FU41 FU12 FU43 Output FIFO Output FIFO Output FIFO 6

7 dr.simon.adaptive Architecture Evolvable Hardware 7

8 Current Projects: SMART SMART Secure, Mobile visual sensor networks ARchiTecture High Security, very low power consumption, and video processing in reconfigurable sensor networks for video applications 8

9 SMART. High Performance Reconfigurable Architecture for WSNs SPI/I2C Digital sensors SPI ADC Spartan-6 FPGA UART Embedded MICROBLAZE MPMC EMC_MCH I2C To PLB Bridge PLB To PLB Bridge uc WSNs with Multimedia capabilities FPGA Dynamically Reconfigurable Nodes 3 different wake-up modes Low Power Design with power islands PLB SPI/I2C Power Management MICROBLAZE HW_ICAP ICAP 9

10 SMART. Minimum Power Reconfiguration for WSNs FPGA core consumption Initial Configuration Static Mode Optimal Reconfiguration Strategy for Reducing Power Consumption time vs FPGA core consumption FPGA core consumption Initial Configuration Shutdown Mode Initial Configuration Double Step Mode time Fast Initial Partial Configuration Fast Initial Partial Configuration time 10

11 SMART. Low Level Reconfiguration Engine BUS Input/Output Registers PLB Bus Data_FIFO _sm Enhanced Icap_control Interface FPGA COMMANDS package Commands _Gen_sm Matrix_sm FPGA Architectural package Reconfiguration peripheral to be integrated within a SoC. Easily portable among different families of FPGAs Support ICAP overclocking (Reconfiguration at 250MHz for Virtex-5). World Record with reallocation Icap_statemachine Xps_HwIcap IPIC-IF Xilinx HwIcap Icap_virtex5/ Icap_Spartan-6 11

12 RECINTO Project. The interoperability problem Provided by manufacturer Not provided by manufacturer System level CAD tools Hardware design tools HDL Physical level CAD tools New needs to work at physical level. Know how to modify directly bit-stream to work with it. Approach to lowlevel design on FPGA s. Development of new CAD tools to improve the design-flow. Result Enhance design methodologies and reduce the cost of adapting working designs to new FPGA families 12

13 RUNNER Project. An industrial reality Today 3D vision kits for academic mobile robots Some products are making a 3D vision revolution Source: Surveyor Corp, 2009 But PC-based computing is not that embedded Real-time applications demand: > 100x performance < 100x energy consumption < 10x size RUNNER consortium To develop HW implementations of 3D vision algorithms Implement them on embedded FPGA systems Use them on a reconfigurable architecture in order to have same flexibility as in SW 13

14 fastcuda Project New Ideas/Projects Proposals Tool support Dynamic Partial Reconfiguration HDL DESCRIPTION FPGA FAST CUDA DESCRIPTION GPU 14

15 DREAMS Project New Projects Proposals Dynamically Reconfigurable Emdedded Platforms for Networked Context-Aware Multimedia Systems To combine many-core and reconfiguration Heterogeneity PLAN NACIONAL de I+D+i Increasing Complexity Design methods and tools, able to cope with complexity and heterogeneity. HW/SW platforms based on different strategies, with advanced features in terms of adaptability, connectivity, etc. Multimedia and secure system that can be adapted to the environment. 15

16 THANK YOU FOR YOUR ATTENTION Universidad Politécnica de Madrid