CAD for VLSI Design - I. Lecture 21 V. Kamakoti and Shankar Balachandran
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1 CAD for VLSI Design - I Lecture 21 V. Kamakoti and Shankar Balachandran
2 Overview of this Lecture Understanding the process of Logic synthesis Logic Synthesis of HDL constructs
3 Logic Synthesis What is this? Process of converting a high-level description of the design into an optimized gate-level representation given a standard-cell library and certain design constraints. Standard Library or Technology Library It can have basic logic gates (cells) like and, or etc. It can have macro cells like adders, muxes and flip flops
4 Objectives Computer Aided logic synthesis tools have greatly reduced the design cycle time and improved productivity. Designers write technology-independent, highly abstract high-level descriptions and produce technology-dependent, optimized gate-level netlists. Both combinational and sequential RTL descriptions can be synthesized.
5 Evolution The designer s mind was the synthesis tool. Design constraints remain the same such as timing, area, testability and power. Manual iterations were done before the gate-level netlist met the design constraints Focus was to generate optimized netlists manually
6 Architectural Description no Partitioning into Higher level blocks Designer s mind Gate-level Representation Meets Design Constraints yes Optimized Gate-level Representation Design Constraints Standard Cell Library (Technology dependent)
7 CAD Synthesis Tools Shift focus to Architectural trade-offs High-level description of the design Accurate design constraints Optimization of the cells in the standard cell library Iterations and generation of the optimized gatelevel netlist is done by the Synthesis tool.
8 Architectural Description no High-Level Description Computer-Aided Logic Synthesis Optimal Gate-level Netlist Meets Design Constraints Place and Route yes Design Constraints Standard Cell Library (Technology dependent)
9 The Impact Before Automation Prone to human errors, especially larger designs No foolproof method of verifying design constraints at an early stage If design constraints not met, then huge time for this back annotation If timing has to be improved, say from 20ns to 15ns, requires total redesign (What-if scenarios) Design reuse was not possible technology specific.
10 The Impact After Automation Designs described like higher level of abstraction and hence less prone to errors. High-level design can be done caring less for design constraints Design reuse, solving What-if scenarios, and in general turnaround time for redesign/back annotation are significant benefits to the designer.
11 Verilog HDL Synthesis Synthesisable Constructs In general, any construct that is used to define a cycle-by-cycle RTL description is acceptable to the logic synthesis tool. Most synthesis tools can convert designs specified using a combination of data flow and specific behavioral constructs. Behavioral synthesis tools that convert a behavioral description into an RTL description are slowly evolving.
12 Synthesisable Verilog Constructs Construct Type ports parameters Module definition Signals and variables Keyword or Description Input, inout, output parameter module wire, reg, tri Notes Vectors are allowed
13 Synthesisable Verilog Constructs Construct Type Keyword or Description instantiation Functions and tasks procedural Module instances Primitive gate instances function, task always, if, then, else, case, casex, casez Notes Eg. my_mux m1(out,i0,i1,s); Timing constructs ignored initial is not supported
14 Construct Type Procedural blocks Synthesisable Verilog Constructs Keyword or Description begin, end, named blocks, disable Notes Disabling of named blocks not allowed Data flow assign Delay information is ignored loops for, while, forever while and forever loops must clk) clk)
15 Synthesisable Verilog Operators All arithmetic, logical, relational, equality (except ===,!==), bit-wise, reduction, shift, concatenation and conditional are synthesisable.
16 References Chapter 14 Samir Palnitkar Verilog HDL.
17 Questions and Answers Thank You
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